Archive for the 'CPU of the Day' Category

August 24th, 2022 ~ by admin

The Soviet CMOS 8085 CPU: 1821VM85A

Omitting the history of the creation of the first microprocessors (such as the 4004) , let’s turn to the moment when 8-bit microprocessors (Intel 8080 and  8085, Motorola 6800 and Zilog Z80 ) firmly conquered the market. It was the time of the second half of the seventies in the last century. It became obvious to specialists that the future belongs to microprocessors, and if you do not invest in these technologies, you will simply fall out of the number of the developed countries. This was well understood by the advisers to the leaders of the USSR at that time. But they also understood that, since the countries of the Eastern Bloc were somewhat late in this work from US, it would be wise to copy the microprocessors already developed overseas. After all, these microprocessors have already solved many of those problems that would take months and years to solve on their own, not to mention huge monetary costs. (It should be noted that the Soviet Union had its own original developments. For example, the 587 series microprocessor kit, this included three microcircuits.)

587IK1 587IK2 587IK3

At that time, it was not clear which chip needed to be copied – Intel, Motorola or Zilog. Each of them was good in its own way, and it was impossible to predict the outcome of the competition between them. In the end, it was decided to copy all microprocessors. And in order not to scatter forces, the enterprises of the USSR were entrusted with copying Intel products. Little Bulgaria got Motorola and Zilog chips were copied in East Germany. This is how Intel, without investing a single dollar, conquered the Soviet market. Microprocessors and microcontrollers under the names 580IK80A (8080A), 1821VM85A (80C85A), 1816VE48 (8048), 1816VE51 (8051)  became native to Soviet electronic engineers.

1821VM85A

The hero of this article is the 1821VM85A-8 bit microprocessor, a functional analogue of Intel 8085A (but in CMOS). It has been developed since the beginning of the 80s at the Novosibirsk plant of semiconductor devices. Production began in 1985. According to Wikipedia, the manufacturing technology is CMOS, 3 microns. According to other sources 0.7 microns, silicone-on-sapphire. Clock frequency – 5 MHz. Theoretically, it can work at a higher frequency.

The die contains about 6500 transistors. When copying the 80C85, several schematic and topological errors were corrected. As a result, the analogue saves stored data without a minimum clock, but the original does not. This manifests itself when the clock frequency changes. When it is reduced to zero, the microprocessor falls asleep, but the contents of all registers remain unchanged. When clocking resumes, the microprocessor continues to execute the program from where it left off.

It was produced in both ceramic and plastic 40-pin DIP packages.

IM1821VM85A – 1990

IKM1821VM85 (tin pins) – 2012

military grade M1821VM85A – 1993

KM1821VM85 – 1991

IKR1821VM85A – 1994

KR1821VM85A – 1996

At the beginning of the marking of microprocessors, the letters I (И), K, M could be used. I did not succeed in finding out the meaning of the letter I (И) in the marking. Sometimes the letter A is missing from the microprocessor name. The letter I (И) is often present in the marking of the chips of the Novosibirsk plant of semiconductor devices. Here is an example of a microcontroller from this manufacturer.

IKM1850VE39 – 80C39 MCU from 1991

Marking the production date on chips was done in two ways. The first is the usual one, consisting of four digits. The first two digits are the year of manufacture, the second two digits are the week of that year. The second marking method corresponds to this table.

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June 30th, 2022 ~ by admin

Chip of the Day: Soviet 573RF10 – a CMOS 8755A

Intel released the i8755 in 1976, the i8755A in 1977 (with better compatibility with the 8085A and 8086/8). The Intel 8755 is an UV- erasable and electrically reprogrammable ROM (UV-EPROM) and I/O chip. The EPROM portion has 16 384 bits, organized as 2048 words by 8 bits. The I/O portion has two general purpose I/O ports, each I/O port is individually programmable as input or output.  These were essentially a combination of the 8255 PIO and the 2716 EPROM on a single die/package. These were made on a NMOS process.

Intel C8755-8 – 1977

Intel C8755A – 1979

NEC D8755AD -1981

Toshiba TMP8755AC ’83

NEC and Toshiba released similar microcircuits behind Intel. Basically, the microcircuit was intended to work together with the 8085A microprocessor. It differs from its predecessor i8080A in that it has a multiplexed data and lower address bus. The standard three-bus architecture of the microprocessor system is obtained by multiplexing with the help of an additional external register. In this register, the low byte of the address is fixed by the special output signal of the microprocessor.

Intel 87C75PF Engineering Sample – 1988

By 1988, the 8755A was obsolete and Intel released the 87C75 instead (see article on the CMOS 87C75).

Novosibirsk IM1821VM85A – 1989

Around this time, the production of an analogue of the i8755A, the 573RF10 microcircuit, began in the Soviet Union. Why start producing a microchip that the world electronics leader is changing to a more advanced one? The fact is that at the beginning of 1988, the production of IM1821VM85A began in the USSR. This was a radiation hard analogue of the CMOS i80C85A. It was with it that the 573RF10 was supposed to work.

K573RF10E (gold pins) 1990

KM573RF10 – Gold ’92 / tin pins ’93

The chip is made in a 40-pin side-brazed ceramic DIP. Supply voltage +5 V. Programming voltage +21 V. It was produced at the Vostok fab in Novosibirsk on a CMOS process (to match the 80C85A).

Unmarked 573RF10

The 573RF10 is the only CMOS chip in the 573 series.

573RF10 die – single memory cell – radiopicture.listbb.ru

Intel 8755A die – 2 memory cells – cpu-galaxy.at

It is noticeable to the naked eye that the 573RF10 is own Soviet development. The 573RF10 and i8755A dies are completely different. The i8755 has two memory arrays clearly visible, while the 573RF10 has only one.
It must be said that the application of the 573RF10 chip was not wide enough. And in general, the idea did not take root. The next obvious step in evolution was the combination of a microprocessor, ROM and RAM, input-output ports in one chip which was frequently done on the MCS-48 and MCS-51 series MCU’s which were also being produced in the Soviet Union at the time.

Written by guest author Vladimir Yakovlev
Edited/Formatted by John Culver – The CPU Shack Museum
Pictures – The CPU Shack Museum and others

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June 13th, 2022 ~ by admin

The History of Angstrem Memory IC’s in the USSR

This article is about memory chips manufactured by one of the entities – the leader of the electronic industry of the USSR – Angstrem. As you know, the Soviet Union ceased to exist in December 1991. We restrict ourselves to the development period of the considered memory chips produced at Angstrem, the end of 1991. Let’s make an attempt to track how the capacity of memory chips grew, how technologies were improved that allowed the Soviet Union not to let the world leaders in electronics go far from itself at that time. A small example: Angstrem’s Dynamic RAM 4K went into mass production in mid-1975, Intel introduced its own in 1974. Intel launched a 16K DRAM in 1977, and Angstrem released its counterpart in 1978.

Angstrem Headquarters

Angstrem was established in June 1963 in Zelenograd (outside of Moscow) as a pilot plant in conjunction with the Scientific Research Institute of Precision Technology. At Angstrem, new technologies for the production of microelectronics were developed, and pilot batches of new microcircuits were also produced. The debugged production technology was then transferred to other enterprises of the USSR and countries of Eastern Europe.
The development and manufacture of memory chips was one of the main activities of Angstrem. It was on them that new semiconductor structures and production technologies were more effectively worked out, and the stability of obtaining finished products is considered in world electronics as a sign of technology ownership. It’s relatively easy to make a small batch of good chips, it’s hard to make a process whereby a large amount of chips can be made and be reliable. It was the very low chip yield percentage that played a cruel joke on Angstrem when mastering the production process of the DRAM 565RU7 chip.

SRAM

In 1966, Angstrem created the first MOSFET in the USSR, which was the first step towards the strict goal of creating CMOS integrated circuits. The first CMOS microcircuit, created in the Soviet Union in 1971, was the 16-bit Angstrom matrix of memory cells 1YaM881.The supply voltage is 6 volts instead of 5 volts, like the rest of the chips in this series.

1YaM881 – 1972

The next in a series of static RAM chips was the CMOS K561RU2 (K564RU2), released in 1976. 564 series of chips is a “military” analogue of the 561 series. In these series, there are several dozen microcircuits. The chip has an organization of 256 words by 1 bit.

561RU2 die – 16×16 256bit matrix clearly visible – The image is taken from the site https://radiopicture.listbb.ru/ with the permission of the author.

It contains 2067 integral elements. Supply voltage is 3-15 volts. It’s an analogue of CD4061A.  It should be noted that in most cases ‘analogue’ means similar to, not an exact copy or exactly compatible.  The USSR did make some compatible IC’s, but they mostly made stuff that was similar, but built to their own specifications/needs.


K564RU2A -1978

K561RU2 -1979

The package of the K561RU2 chip is wider than the standard packages of this series.

K565RU2 -1979

The K565RU2 static RAM chip was manufactured using NMOS technology. Chip capacity was 1024 bits (1024×1). Contains 7142 integral elements. An analogue of Intel 2102A, developed in 1974. K565RU2 appeared in 1977. It was originally designed to be placed in a ceramic package, but later, in order to reduce the cost of production, the dies began to be packed in plastic packages.

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June 5th, 2022 ~ by admin

CPU of the Day: P.A. Semi PA6T PowerPC

When Apple bought P.A. Semi back in 2008 it was the beginning of the era of the iPhone, and their was much speculation as to why Apple was buying a company that made low power high performance PowerPC processors.  Especially since the iPhone ran on ARM and the Mac had moved from PowerPC to x86.

P.A. Semi PA6T-1682M

P.A. Semi was started in 2003 by Daniel Dobberpuhl (who passed away in 2019).  Dobberpuhl was one of the truly greats of microprocessor design, with a career starting at DEC on the T-11 and MicroVAX, before helping DEC transition to the Alpha RISC design (21064).  It was Dobberpuhl who started the design center in Pal Alto (where P.A. Semi would later take its name from) that designed the DEC StrongARM processor.  A processor that was later purchased by Intel and became the XScale line of ARM processors.

After Intel bought the StrongARM line, he then helped start SiByte, making MIPS based RISC CPUs, and continued to do so when SiByte was purchased by Broadcom. So when he started P.A. Semi it was less about PowerPC and more about RISC, PowerPC just happened to be the architecture they chose to use.  The design team had extensive experience on a variety of CPU architectures, including SPARC, Itanium, and the early Opterons.  You can see why this acquisition was so attractive to Apple.

PA6T block diagram

In the few years (2003-2008) from when P.A. was founded to when Apple took them over, they did design, market, and sell a PowerPC processor line called PWRficient based on what they called the PA6T core.  The PA6T-1682M was a Dual core PowerPC processor (the 13xxM was the single core version) with each core running at up to 2GHz with 64K of L1 Instruction cache and 64K of L1 Data cache.  They were fab’d on a 65nm process by TI and ran at 1.1V.  The L2 cache was scalable and shared amongst the cores.  In the 1682M this was a 2M 8-way cache with ECC.  One of the most useful features was their clock stepping.  They could drop to 500MHz at only a few watts per core, and then back up to the full 2GHz in 25us.

AmigaOne X1000 (made by Aeon) PA6T-1682M

The PA6T was only on the marked for a few months (from the end of 2007 to April 2008) before Apple bought them for $300 million, but in this time P.A. Semi had numerous design wins.  Amiga selected it for use in the AmigaOne X1000 computer.  The AmigaOne did not hit market until 2011, which means that while P.A. Semi was bought and completely under control of Apple, they still continued to make, support, and supply their previous customers with the 1682M CPU.  Certainly Amiga wouldn’t be big enough to push Apple to continue making a chip?

They were not, but others were, and the PA6T was such a great processor that it had been selected and designed in to many computer system used by US Defense contractors, and if anyone doesn’t like change, its Defense contractors, so with some prodding by the US Dept of Defense Apple continued to make (or rather have TI make) the PA6T processors.  Curtis-Wright had designed the PA6T into their new CHAMP-AV5 DSP VME64 board, which was used for signals processing across numerous military applications.  They also also used the PA6T (at 1.5GHz) in the VPX3-125 SBC. Themis computers, NEC, Mercury and others designed in the PA6T. Extreme Engineering, another maker of PA6T based boards, referred to the design as ‘ground breaking.’

Extreme Engineering XPedite8070 SBC

It would have been interesting to see what P.A. Semi could have achieved had they not been gobbled up by Apple.  Clearly we see the results of the talent of the P.A. team in what Apple was able to accomplish with their A-series processors, but clearly P.A. had something special for the PowerPC architecture as well.

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January 7th, 2022 ~ by admin

The Many Sockets of VIA CPU’s

C5M – Ezra-T Prototype Pathfinder – PGA370

Most are familiar with the history of VIA so we won’t dive extensively into that but a quick summary is in order.  VIA was founded in California in 1987 before moving to Taiwan, and previous to 1999 was well known for making chipsets and other support chips for computers.  In 1999 VIA bought both Cyrix (from National Semiconductor) and Centaur Technologies (from IDT, who made the Winchip series of processors.

These purchases did two main things for VIA, it first gave them access to the x86 architecture, and it gave them legal leverage to continue down the x86 road.  Cyrix possessed a license to the P6 processor bus (through a cross licensing with Intel) that was good until 2006.  This allowed VIA to make what became the Centaur based CyrixIII/C3 processor on the P6 based Socket 370 platform. These are the processors and socket we are most familiar with for VIA CPUs.  With clock speeds of 466-1.2GHz and eventual support for the Tualatin based boards these chips were the most ‘public’ facing CPUs.  VIA also of course made many BGA versions, used in ITX form factor, and other mini type systems.

CNA – Isaiah – Interestingly using the old Pentium III-M pin out

The VIA designs, despite originally being called ‘CyrixIII’ were all based on the Centaur designed core.  Intel, as was its custom, sued VIA in 2001 asserting patent infringement, which it is likely VIA was expecting.  As with the case of Intel and Cyrix, VIA countersued, asserting Intel was infringing on patents VIA had acquired with the Centaur deal.  In 2003 a settlement was reached that included a 10 year patent cross license between Intel and VIA and allowed VIA to continue to make x86 compatible processors (extended in 2013 by 5 years until 2018(.  The deal also granted VIA a 4 year (with an extra optional year) license to continue to make chipsets compatible with Intel processors (they had originally signed a deal in 1998 to allow VIA to do so. This is how we continued to get VIA chipset based motherboards for Intel processors.  The deal also added a small detail that leads to todays discussion, it granted VIA a 3 year grace period to continue making bus and pin compatible processors up through 2006.

C5J (Left) and C5R (Right) – Banias Compatible Pentium M pin out

This last part is interesting, the fact that it was a grace period means it reflected what VIA was currently doing, not what they were planning to do in the future.  The obvious example here is the C3 line on Socket 370 using the P6/Tualatin bus, but that was pretty old news in 2003 so what was VIA working on?  CPU’s on more modern sockets of course, namely Socket 479 (mPGA479M) used by the Pentium-III-M (Tualatin) and Pentium M (Banias/Dothan).  These use the same physical socket on a motherboard, but the keying pins are different on the CPUs themselves.  These are all mobile designs which lend themselves well to VIAs low power designs.  VIA did also make several reference boards for these CPU’s so its clear that there was plans for releasing them to the broader market, and likely with additional motherboard support.

C5J (Left) and C5R (Right) – C5R is a 110nm part with a slightly larger die the the C5J

Another socket was just being developed at the time of this agreement, and that is perhaps the most interesting.  Intel LGA775 chips began sampling in late 2003, which is after the grace period of 3 years had begun so it would make sense for VIA to not develop CPU’s using a socket they were going to lose access to in a few years.  The package likely was in development for a couple years prior which is likely why VIA made a few (likely VERY few) samples for it.  The samples are marked C5R which is a C7 Esther core, if VIA’s naming is consistent, this would be the TSMC 110nm version of the 90nm C5J.

C5R With heatspreader and with heatspreader removed.

The Esther core code names are a bit confusing because of how some CPUID programs identify them. X-86-guide.net has a quite nice ID guide that goes into some great detail on them.  In summary there was a 90nm Rev A C5J made by IBM, and later a 90nm C5J (called Rev D) made by Fujitsu with some additional features.  This Rev D part often gets identified as a C5R, or a C5J shrink, neither of which is correct.  The actual C5R (and related C5Q) were what appear to be backup plans for the IBM produced parts, using a larger 130/110nm process at TSMC. Looking at the mPGA479 unfinished packages (labeled C5J and C5R) the die attach area on the C5R is actually slightly LARGER then the C5J (~35mm2 compared to 28mm2 of the C5J)

C5R Esther – 110nm TSMC in LGA775

Most VIA samples are labeled with the code name in Cxx format and not the marketing code name (Esther Isaiah etc) as each of the Marketing code names (for lack of a better term) consisted of many actual sub-cores.

Code Code Name Process Die Size
(sq. mm)
Notes
C5A Samuel TSMC 180nm 75
C5B Samuel 2 TSMC 150nm 52
C5C Ezra TSMC 150/130nm 52
C5M Ezra-T TSMC 130nm Proto Only (Pathfinder)
C5N Ezra-T TSMC 130nm 56 Cu Interconnects – Low-k – Tualatin Bus
C5X Nehemiah TSMC 130nm 78 10% Faster then C5XL – Higher power
C5XL Nehemiah TSMC 130nm 52 133FSB
C5XP Nehemiah Low Power C5XL – Not released
C5P Nehemiah TSMC 130nm 47 200FSB – DP Support
C5Y Nehemiah Unreleased – Adds SSE2
C5Z Nehemiah Unreleased – VIA V4 System Bus
C5I Esther 90nm Initial Esther – Almost Taped out
C5J Esther Rev A 90nm IBM
Rev D 90nm Fujitsu
C5Q Esther TSMC 130nm Unreleased
C5R Esther TSMC 110nm Unreleased – Samples Made
C5W Esther IBM 90nm SOI Canceled early
CNA Isaiah Fujitsu 65nm VIA Nano 1000/2000
CNB Isaiah Fujitsu 65nm VIA Nano 3000
CNQ Isaiah TSMC 40nm VIA Nano X2 4000 VIA Eden X2 4000, VIA QuadCore E U4000 / L4000 – (two die VIA Nano X2 or VIA Eden X2)
CNR Isaiah TSMC 28nm VIA QuadCore E – C4000, VIA Eden X4 C4000

Looking at the table above we can see VIA took many roads in the development of their CPUs, with many that went nowhere.  Some may see this as a lack of direction or focus, but in a lot of ways VIA seemed to be trying to figure out the best CPU for the market at the same time they were trying to make the best CPU from an engineering standpoint.  Where these two paths converged you had a marketable CPU that made it into mass production, and where they didn’t, or where legal road blocks arose, the design was canceled.  VIA’s CPU development is even more obscure now, though they have made a few other designs we will cover in a later article, as well as the return of Intel to the VIA party.

 

 

 

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November 20th, 2021 ~ by admin

The Soviet 1801VM3 Enhanced LSI-11 Processor

This is turning into a bit of a series on Soviet processors.  Continuing from our article earlier on the 1801VM2 LSI-11.  The 1801VM3 is the further development of 1801VM1/VM2 and is the highest performance microprocessor in 1801 series. It’s a 16-bit single-chip microprocessor that includes an operating unit, a firmware control unit, an interrupt unit, a memory controller and Q-BUS control unit. A distinctive feature of 1801VM3 is a large amount of addressable memory (4MB vs 64K for the 1801VM1 and 64k+64K for the VM2), high performance and ability to connect a floating-point coprocessor 1801VM4.

1801VM2 die

1801VM3 Die

1801VM3 Specifications

  • Number of processor Instruction: 72 Fixed Point and 46 Floating Point (with 1801VM4 FPU)
  • Address Space: 4MB
  • General Purpose Registers: 8
  • Manufacturing process: 4 micron N-channel silicon gate MOS technology (later migrated to 3 micron)
  • Die size 6.65 × 8 mm
  • Transistor count: 28,900 active transistors, 200,000 integral elements
  • Clock rate: 4MHz  (1801VM3V) 5MHz (1801VM3B) 6MHz (1801VM3A, upgraded to 8 in 1991)
  • Performance: For register based operations (like addition) up to 1,500,000 instruction/s (1.5 MIPS)
  • IRQ Lines: 4
  • Supply voltage + 4.75V-5.52V
  • Power consumption: 1.7-2 W
  • Packages: CDIP64 (KM1801VM3) LQFP64 (KA1801VM3) CQFP64 (KN1801VM3/N1801VM3)

Like the VM2 before it the speeds were denoted by a series of dots on the package (or lack thereof)

KM1801VM3A – 6MHz (no extra dot) CDIP64 package from 9008

KM1801VM3B – 5MHz (one extra dot) CDIP64 package from 9003

KM1801VM3V – 4MHz (two extra dots) CDIP64 package from 9202

 

KA1801VM3 – 8MHz (no extra dot – post 1991) PQFP64 package from 9108

N1801VM3 – 8MHz (no extra dot – post 1991) CQFP64 package from 9324 – Remarked from a military part (rhombus marking marked over)

 

The KM1801VM3 appeared as part of the DVK line of computers, starting with the DVK-3M model (PCB ”Electronics МС 1201.03” and “Electronics МС 1201.04”).  Using the same ISA (Instruction Set Architecture) allowed DVK (and others) to rapidly update their computer line when new processors were available, and allow for a wider software base.  This is very much like the original IBM PC using the x86 architecture.  The transition from 8086 to 80286 was relatively easy to design, and nearly seamless for the end user.

DVK PCB Electronics МС 1201.03 board on the top.

Many devices built on the basis of the 1801 series CPU contain other microcircuits of the same series (support circuits).
In addition to microprocessors, this series includes:
– ULA 1801VP1-xxx
– masked ROM 1801REх-xxx
– EEPROM 1801RR1

ULA and EEPROM

The 1801VP1-xxx is a ULA- (Uncommitted Logic Arrays). It’s made using a 3 micron N-channel silicon gate MOS technology with one metal layer. First, base silicon wafers are made that contain transistors. These are doped regions of silicon and a separate oxide-insulated layer of polysilicon gates. Then all this is covered with an oxide layer. Base wafers are ready.

In this form, the wafers can be stored for a long time or transferred to another fab. All 1801VP1-xxx chips, regardless of number, have the same structure and arrangement of transistors. And they are made on the same base wafers.

KR1801VP1-22 die

Differences between the chips appear only at the last stage of manufacturing. In the upper oxide layer, the die is etched by photolithography to access the required transistors. And then form a metallic pattern from aluminum. This pattern defines the electrical circuit. The number in the marking identifies the purpose of the chip. For example, 1801VP1-033 is an external device controller.  This is similar to how a MaskROM is made but instead of only memory elements, it contains logic elements allowing for a custom IC to be made (like a mask programmable PAL/GAL)

KR1801VP1-119

The 1801VP1-119 is a companion chip for 1801VM3. It can be said to be the “north bridge“.
The 1801VP1-119 performs the following functions:
-forms control signals for DRAM;
-forms control signals for system SRAM;
-generates signals to select system ROM;
-generates control signals for detection and correction of memory errors (EDC) using Hamming code (555VGH1). Error correction circuits reduced performance by 10-15%. Therefore in some computers, there were jumpers to enable/disable the EDC
-buffer data register control;
-generate other signals

This was the beginning of what would be come chipsets, replacing loads of TTL with custom circuits.  The exact same evolution was occurring in the west with the PC environment, until nearly all the support circuits were integrated into just a couple large ASICs.   Its interesting to see the development paths of the Soviet computers and the West.  While they were entirely different instruction sets, they evolved in very much the same way.  East or West, LSI-11 or x86, at the end of the day, a computer is a computer and will evolve in similar fashion.

 

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November 4th, 2021 ~ by admin

The Soviet 1801VM2 LSI-11 Processor

The Soviet-made 1801VM2 CPU (a binary-compatible implementation of the PDP11 instruction set and QBUS interface) was developed in 1982. The 1801VM2 is a further development of the earlier 1801VM1 doubling the original 5MHz clock speed. From a constructive standpoint this CPU is a completely independent development.

1801VM2 die

1801VM2 die – 1983 dated

1801VM2 Specifications

  • Number of processor Instruction: 72
  • Manufacturing process: 4 micron N-channel silicon gate MOS technology
  • Die size 5.3 × 5.35 mm
  • Transistor count: 18,500 active transistors, 120,000 integral elements
  • Clock rate: Up to 10 MHz
  • Performance: For register based operations (like addition) up to 1,000,000 instruction/s (1 MIPS) – for operations like multiplication, up to 100,000 instructions/s
  • Supply voltage + 5V
  • Power consumption: up to 1.7 W
  • The case is 40-lead, ceramic DIP (KM1801VM2) or plastic DIP (KR1801VM2). (a surface mount version was also made)

To increase noise immunity in comparison with 1801VM1, additional ground contacts were made for the address / data bus.
The 1801VM2 was manufactured at two factories: Angstrem and Solnechnogorsk Electromechanical Plant (SEMZ).  As was typical of the time speed grading was done by adding extra marking to the chips post-testing.  Its very easy to miss these, if a chip was tested at 10MHz and passed it received no extra marking and was considered an 1801VM’A.’  If the device failed at 10MHz but ran at 8MHz a small dot was added to the package (and was considered a grade ‘B’ device).  This dot was not to be confused with the dot for the pin one marker, though often placed…next to it.

Ceramic DIP 1801VM2A Angstrem – 1989 No extra dot

Ceramic DIP 1801VM2B Angstrem – 1987 – Note the extra dot in this case by the date code

Plastic DIP 1801VM2A Angstrem – 1990

KN1801VM2- Angstrem 1985 CQFP Surface mount version (image Baator)

Ceramic DIP 1801VM2 Solnechnogorsk Electromechanical Plant – 1990 – Extra dot by pin 1 marker

In comparison with 1801VM1, expanded arithmetic instructions (MUL, DIV, ASH, ASHC – part of a the set of PDP-11 EIS), and also operations from the floating point instruction set (FIS) were added. The FIS instructions (FADD, FSUB, FMUL, FDIV) are realized through subroutines – when performing these instructions there is a special type of interrupt and the program handler in memory (“shadow” system ROM K1801RE2) of the console mode is executed, a ‘firmware’ style of FIS implementation, as its not truly hardware (the ROMs break down the FIS instructions into something the 1801VM2 can execute)
During the design of the microprocessor, a microcode error was made, leading to a malfunction of the processor when reading with addressing method 17 ( MOV (PC), R0).

DVK-1 Computer

The 1801VM2 was the heart of a number models of DVK computer. DVK was developed at the Research Institute of Precision Technology , Zelenograd (just outside of Moscow). The first model DVK-1 was developed in 1981, and released in 1983. Architecturally DVK copies mini-computers from DEC PDC-11 and PDP-11. By 1990, 200,000 DVK computers of the nine different models were produced.

Romashka Word Processor

Use of the processor continued well into the 1990’s. The “Romashka” belonged to the latest generation of electronic typewriters, which in their functionality were close to computer text editors. This typewriter made it possible to automatically format text (set alignment, change the spacing between characters and between lines, use bold and underlined fonts, etc.) and had an electronic memory of at least one page (3800 bytes).  In the West these half typewriter half computer were called Word Processors, and were quite popular through the 1980’s.   The machine’s control unit was a microcomputer based on the KM1801VM2 processor.
“Romashka” was produced by the Kursk PO “Schetmash” in the first half of the 1990s.

“Electronics IM-05 “- Soviet chess computer, contains 1801VM2 inside. It was a continuation of the line of chess computers “Electronics”. Produced by the Svetlana Association, Leningrad.

In 1984, the military-grade microprocessor 1806VM2 was released.
This microprocessor functionally corresponds to the 1801VM2, but is made using CMOS technology.

  • Clock rate: up to 5 MHz
  • Number of Instructions: 77
  • Contains 134,636 integral elements
  • Power consumption: up to 0.025W

The 1806VM2 developers fixed the microcode bug present in 1801VM2 (much to the relief, or annoyance of programmers). The 1806VM2 was supplied in a 42-lead dual in-line ceramic package with flat leads, N1806VM2 in a 64-lead CQFP. The rhombus marking on the chips denotes a military-grade device.

1806VM2 – Angstrem 1991 in the nice pink flat pack

N1806VM2 – Angstrem 1999 in a Ceramic quad flat pack

CQFP N1806BM2 on a ceramic substrate forming a military Single Board Computer – circa 1987 (image Baator)

These 1806VM2 are still being made by Angstrem, if you need to build a PDP-11 computer to run Tetris on, or repair a Buran shuttle you may have laying around.

In 1990, a radiation-hardened microprocessor was introduced, compatible with the 1806VM2, known as the 1836VM2/N1836VM2.  Just like in other countries, existing code base and known reliability are more of a driver of what the military/industry uses than having the latest and greatest.  There are still MIL-STD-1750A processors being made and used, rad-hard 8051s and 80186s, and Soviet PDP-11 processors right there with them.

Photos of microprocessors from the collection of Perfiliev Andrey (Andreycpu).
Article written originally by Contributing Author Vladimir Yakovlev (edited by cpushack)

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September 28th, 2021 ~ by admin

The RCA Solid State Technology Center (SSTC)

TCS008 Adder – TCS017 FPU Control and TCS060 Shift Register – 1974-1975

Today most chips we use are made in CMOS (Complimentary Symmetrical Metal Oxide Semiconductor), which is a process using both p-type and n-type MOSFET transistors.  It was invented back in 1963 by Fairchild, but was commercialized by RCA in 1968 with the introduction of the CMOS based 4000 series of MSI logic devices.  These were basic IC’s with such things as NOR gates, Adders, Flip flops and the like.  A CMOS equivalent to TI’s popular TTL based 7400 series.

RCA also made a series of computers in the 1960’s (to compete with IBM) as well as other electronic products. including many for the US Air Force, NASA and US Army.  In 1970 RCA created the SSTC (Solid State Technology Division) in Somerville, New Jersey to develop CMOS processes (and Silicon on Sapphire versions) into more commercial products. At the time most IC’s (outside the 4000 series) were made in PMOS or NMOS, CMOS was considered too slow, despite is lower static power usage and high noise immunity.  SSTC was to develop processes, standard, and eventually devices, that RCA could then commercialize and/or use in their other products (such as their computer line, radios, and military products).  It was out of this project that the famous COSMAC processors (CDP1801 and CDP1802 line) came from.

TCS002 16×16 Multiplier 200ns – Note the hand written characterization markings – 670uA @ 5V

SSTC also made a series of essentially standard test devices.  These were based on a common cell architecture (more common in ASICs today) with a series of chips made to demo what was possible with the CMOS-SOS (CMOS on Sapphire) process.  These ‘standard’ IC’s would then be used in various demo products for potential customers.  The most interested customers at the time were the US Air Force and NASA.  The RCA CMOS process allowed for a great power savings, and especially when built on a sapphire substrate, exhibited a high tolerance to radiation, useful for the then rapidly expanding satellite/space market.

AN/GVS-5 Laser Range Finder – 1970’s. They were huge, but very impressive for their day

The first of these chips were made in 1974-1975 and were made with a 7 mil (178micron) standard cell height, on a 20 micron process.  Versions were also made with a 5 mil (127 micron) size, specifically for the military market.   These were not typically commercially available devices, but used internally for test, evaluation, and to build specific products, though the technology used for them was often turned into generic products.

Below is a list of some of these devices SSTC made. The TCS prefix was used to denote these being made by SSC on a CMOS-SOS process.  A TCC prefix is a standard CMOS process.

Device Function
TCS001 16×16 Multiplier
TCS002 16×16 Multiplier 200nsec
TCS008 8×8 Adder
TCS015 18-bit Reclocking Register with complement select
TCS016 Dual 8 -Bit Position Scaler for Floating Point Applications and Other Binary Division.
TCS017 Floating Point Control for FFT Arithmetic Unit of Arbitrary Radix (Parallelism)
TCS026 Floating Point 2×1 Multiplexer – 163 gates**
TCS027 12-bit Up/down counter (8+4) – 300 gates**
TCS029 Unknown**
TCS030 8-bit Adder = 450 gates**
TCS031 9-bit 4×2 Multiplexer – 150 gates**
TCS032 Adder Multiplexer Control – 166 gates**
TCS039 Multiplier
TCS040 Correlator
TCS043 D/A converter (rad hard)
TCS045 Code Generator
TCS047 Frequency synthesizer
TCS057 9×9 Multiplier (8×8 + sign)
TCS060 Shift Register with Variable Length, Complementing Functions and
Switched Delays. Total Registers = 38 Bits
TCS065 9+9 Adder(8+8 + sign)
TCS074 ROM
TCS130 16K SRAM
TCS151 4K SRAM

**Used to build the NASA 32-bit SUMC (Space Ultrareliable Modular Computer)

These were used in many military products such as the AN/GVS-5 handheld laser rangefinder, a Programmable waveform generator used in FM RADARs, and for the imaging system (digitization and compression of video to be sent) in the remotely piloted Lockheed MQM-105 Aquila drone (yah drones, back in 1975).  The Aquila project was particularly challenging, as the circuitry had to be small enough, and low power enough to fit on a small airframe, yet still handle video compression fast enough that a ground station could receive and decode useful imagery.   This was done with several large hybrid circuit modules consisting of many TCS057 Multipliers and TCS065 Adders.  This was capable of 200-1600Kbps data rates, not bad in 1975.

Aquila Artillery Spotting Drone (Lockheed Martin)

Most of the TCS line of components was capable of 10MHz operation while running at 5V, and voltage and clock rate scaled with each other, so they could be clocked lower for less voltage and power usage, or clocked higher at the expense of more power.

It is a bit unfortunately that RCA lost its way in the 1970’s, attempting to became a conglomerate, they became known as Rugs, Chickens and Automobiles (having bought parts of Hertz Rental Cars, a frozen TV dinner company, a carpet company and others).  They were bought by GE in the 1980’s and in 1988 the Solid State Division, with what remained of the SSTC was purchased by Harris Corporation, which continued to make the 180x line of CMOS processors for over 20 years.  If RCA had stayed focused on making CMOS a commercial success, we may have had more and faster CMOS processors nearly a decade sooner.

 

 

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September 1st, 2021 ~ by admin

NEC’s Forgotten FPUs

NEC uPD70108C – V20 CPU – Late 1984

NEC had a cross license agreement with Intel dating back to April of 1976 that allowed each company to make/sell products based on each others patents.  This was particularly important in the 1970’s as having a viable ‘second source’ for your designs was considered critical for it to be viable in the market.  This was especially true for Intel, who wanted to get into the Japanese market. In 1979 NEC began to produce and sell the 8086 and 8088 processors.  NEC wasn’t going to succeed by just being a second source to Intel though, designing their own processors was of great importance.  While producing the 8086/8088 they also began working on their own version, which would be an enhanced 8086/8088 processor.

NEC V30 Die (courtesy Birdman) – 8086 with many enhancements

The result was the rather well known V20/V30 processors of 1984.  These were not just clones of the Intel MCS-86 (though determining this took several court cases and resulted in the Chip Act of 1984).  The V30 had some pretty big differences, notably, internally it had dual 16-bit busses, allowed data to be moved much more efficiently, as data could be moved into and out of a register at the same time (nearly).  It also increased the microinstruction word from 21 bits to 29 bits, added a hardware effective address generator, additional instruction pointers, and a hardware shift/loop counter.  Taking advantage of these features added some new instructions as well, 156 compared to the 8086’s base 133.  The V30/V20 were the beginning of a line of V-series processors.  NEC went on to make  ‘186/188 style processor (the V40/V50) as well as a series of microcontroller versions  (V25/V35 and others).  The V20/V30 were to be supported by a math coprocessor like the 8087 called the upd72091.  Very little info is available on the 72091 as it was cancelled very early on in its design, as by 1984-1985 it was already out of date.  Its replacement was to be a bit more powerful.

Design of the the upd72191 started likely at the same time the V30 was released, around 1984-85, with specifications released in 1986, and plans for chips by 1987.  This chip was in an advanced state of planning, such that many products, including motherboards (such as the Ampro Little Board PC) and industrial controllers designed with sockets for it.  Preliminary datasheets exist, but alas, no chips seem to be found.

LittleBoard PC (Ampro) with support for canceled upD72191 (V40 based)

The upd72191 was made in CMOS and is a bit like an enhanced 80C187 but with support for the V20/V30.  It is fully IEEE-754 compatible (the 8087 wasn’t as the standard wasn’t finished yet) and supports a similar instruction set as the 80C187 (and thus the 80387).  Unlike the 8087 it supports the full set of Exponential, Trig, Logarithmic, and Hyperbolic instructions.  The 8087 was somewhat limited in this, as it was already pushing the limits of what was possible on a single chip at thee time of its release.  The 72191 supports FSIN/FCOS which the 8087 doesn’t and many other functions (its full instruction set could not be found).  The 72191 has a mode pin that selects between interfacing between the V20/V30 and the V40/V50, (as these talked to coprocessors differently) so it was compatible with 4 distinct processors.  The 80C187 could only be used with the 80186 and the 8087 could only be used with the 8086/8088.

upD72191 FPU Block Diagram – 1986ish

Looking at the block diagram of the ‘191 we notice something else, its a dual bus design, much like the V30 processor.  Internally there are a pair of 74-bit busses for the mantissa (fraction) side and a pair of 16-bit busses for the exponent side.  This is a striking difference from that of the 8087 and the ‘187.  The 8087 has a single 16-bit bus for the exponent, and a 64-bit (68-bits into the shifter and ALU) for the mantissa.  There are 3 extra bits for enhanced accuracy, and a extra leading bit that is always 1 for floating point math, giving 64 bits of ‘data’.

The dual bus design makes sense as NEC did the same for the V-series.  Coupled with the right microcode, it can greatly enhance the speed of the FPU.   So why then is the bus expanded to 74-bits for the mantissa?   In the 80187 and 80387 this bus is still only 68-bits.  We look to the design of NECs follow on FPU for the answer.  The upd72291 (and its 32-bit bus 72691 version) are rather different beasts, made for the the V33/V53 x86 CPUs and V60/V70/V80 non x86-CPUs.  We’ll talk about them in more detail later, but they share the same 74-bit mantissa as the 72191, and in this case, the designers wrote a paper on its design.

The FPP [72691] is the only floating point processor that provides the power function xy.  This function (called FPOWER in the instruction set) is difficult to implement not only for its complex definition but also for sufficient accuracy. The equation Xy = e(y*logeX)
does not give good accuracy because the accuracy error of the log function is augmented by the exponential function.  The FPP solves this problem by providing a 74-bit data width for the mantissa data bus.

Being as the 72191 was canceled, the ‘291/691 would in fact have been the only FPU to support this in hardware, but it seems it was first implemented on the ‘191.  The solution only works well for larger (greater then 32) values of y, otherwise iterative multiplication is used, but where it can be used it greatly speeds up the calculation.

When the 72191 was canceled NEC thoughtfully provided a single chip solution called the upd9335C for allowing an 8087 to be interfaced to the V40/V50 processors which, like a 186, used a HOLD/HOLDACK bus release protocol instead of the 8086/8088s (and V20/V30s) REQUEST/GRANT.  For applications using a V20/V30, an 8087 could be used directly.

NEC upD70632R-20 20MHz V70 Processor

In 1989 NEC released the next of the V-series, the V60, V70 and later the V80 processors.  These were a departure from the previous in that they were no longer based on the x86 architecture, but rather a completely new ISA (though the V60 and V70 had a V20/V30 emulation mode).  These were full 32-bit designs, and were Japan’s first widely available 32-bit processors.  Of course with a new processor comes the need for a new FPU and NEC had not one, but 2 FPU options for these.  The upd72291 and upd72691 are based on the same design, but with some major feature differences.  The 72291 is designed to work with processors that have a 16-bit data bus such as the V60.  It also could be used with the older V33/V53 x86 designs.  Internally it has eight floating point registers and supports all your typical floating point functions as well as vector math functions.  The upd72691 is designed for 32-bit data paths, but adds a bit more…

NEC updD72291R-16 FPU

In addition to expanding the register set to 32 FP registers, the ‘691 also added a complete suite of matrix  math functions. The ‘691 was made on a 1.2u CMOS process and contained 433,000 transistors. (nearly 50,000 MORE then the V60 processor) Running at 20MHz it was capable of around 6.7MFLOP and supported 24 vector/matric instructions as well as 22 mathematical functions.  Like the 72191 it had a 74-bit mantissa datapath, but expanded the exponent path to 17-bits to support double extended precision number formats. It is a highly microcoded design using a 3072 word (43 bit word) microcode ROM, 20% for vector/matrix, 37% for arithmetic, and the rest for exceptions handling and other house keeping instructions. Interestingly, these microps themselves encode additional instructions that NEC call nano-ops, these controlled just the ALU operations of the instruction (the rest being bus control and sequencing).  These nano-ops were stored in a 256 word x 74-bit Nano ROM (only 120 words were used, the rest for potential expansion). This was the last of the line of NECs dedicated FPUs (excluding the few MIPS FPUs they made).  Its a bit ironic that it seems they canceled as many designs as they made.

…but perhaps they didn’t?

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August 12th, 2021 ~ by admin

Forgotten Italian CPU – The Genesys B52 MMX

Introduction

On this site you can read about thousands of processors models. And every year it is more and more difficult to write about some new (old) processors, since everything has been known for a long time. But there are also exceptions to the rule which we love to find. In 2021, I learned about one unusual processor, the information about which I want to share with you. The roots of this processor’s history go back to Italy, in the distant year or 1998. This time just falls on the confrontation between Intel and its second generation Pentium and AMD K6-2 and K6-3 processors. The Cyrix MII processors from Cyrix Corporation, IDT WinChip 2s and Rise mP6s were still going strong as well.

But before we talk about the Genesys B52 MMX processor, we should take a closer look at Intel Pentium II processors in general, as the Italian processor primarily owes its appearance to them.

Intel Pentium II

From 1993 to 1997, the Pentium dominated all market segments. Over time, the name of the “Pentium” trademark even grew into a household name (Its all about the Pentiums baby), but with the release of the Pentium II, everything changed. If earlier Intel did not deeply segment the market, there were Pentium Pros for workstations and servers, and for everything else there were various models of Intel Pentium processors, in which, at the end of their domination, Intel added MMX instructions, depriving and thereby putting an end to its server segment. The new slot form factor of the processor, the abandonment of the usual pins and ceramics and further segmentation of the market (using Intel Celeron processors and the new Xeon line) radically changed the further course of development of the history of microprocessors.

May 7, 1997 saw the light of the first models of Intel Pentium II processors, manufactured on a 350nm process with a core voltage of 2.8 volts. The first models were based on the Klamath core (named after the river by which The CPU Shack is located) core, operating at 233 and 266 MHz. The main differences from the Pentium Pro predecessor it was based on were the L1 cache increased from 16 to 32 Kb, and the presence of a block of SIMD instructions called MMX first introduced on the last P55C processors. Like the Pentium Pro it featured its own L2 cache on the module, but in this case it was 512KB fixed on the same PCB as the processor core, a much cheaper solution then the dual ceramic cavity package of the Pentium Pro.

Before the Pentium II, only the Pentium Pro could boast of its own cache, running at the frequency of the CPU core. But, placing the CPU core and L2 cache on the same substrate was an expensive pleasure even for Intel, and the processors had to be cheaper for better competition, which was getting more and more intense. Intel then made a “wise” decision, as a result of which the Pentium II got a its own L2 cache next to the CPU core This engineering solution significantly reduced the cost of manufacturing processors. BSRAM L2 cache chips were manufactured by Toshiba, SEC and NEC at that time, rather then being made in house by Intel, further easing the cost burdens.

Pentium II Klamath SECC1 PBGA Core 2 x Cache on front 2x + TAG on back

For all models of Pentium II processors, the cache size remained unchanged and equaled 512 KB, while different Pentium Pro models had a cache from 256 to 1024 KB. The L2 cache of the first Pentium II processors consisted of four microcircuits located on both sides of the cartridge processor board and operated at half the core frequency. In addition to the processor core and 4 L2 cache chips, there was also a tag-RAM chip on the cartridge PCB, a total of 6 IC’s.

Backside with 2x cache + TAG

The tag-RAM size/configuration determines which range of main memory can be cached. For example, if the L2 cache is 256 KB and the tag RAM is 8 bits wide, then this is enough to cache up to 64 MB of main RAM. However, if you add additional RAM in the process, it will not be cached unless you also expand the tag RAM. On Socket 1-3 486 systems, most motherboards allowed adding and modifying additional L2 cache and tag-RAM chips for this purpose. The Pentium Pro had built-in L2 cache and tags capable of caching up to 4GB of main memory, whereas the first Pentium IIs could cache up to 512MB of RAM.  This was in part to set them apart from the server oriented Pentium II Xeon which had full speed cache capable of caching 4GB (or 64GB with PSE-36),

In January 1998, Intel announced the Pentium II processor, built on a new core, codenamed Deschutes (Another river in Oregon). The processor core was manufactured using the smaller 250nm process, which lowered the operating voltage to 2.0 V, instead of 2.8 V for “Klamath”. The L2 cache of 512 KB still worked at half the core frequency, but it was made in the form of two BSRAM chips located to the side of the processor package. In later modifications of the Pentium II Deschutes core, Intel replaced the tag-RAM chip, thanks to which the processors could cache up to 4 GB of RAM (the 82459AD revision).

The first generation of Intel Celeron processors were based on the “Covington” core were essentially processors on the “Deschutes” core, but without ANY L2 cache. Thanks to this, they had very poor performance, but they overclocked very well, demonstrating the best overclocking figures up to double the nominal clock frequency.

Deschutes core with Organic BGA core and 2x cache chips on front. TAG on back

All overclocking of Pentium II, as a rule, rested on the characteristics of microcircuits used by BSRAM and tag-RAMs. The latter, like the cache, was much disliked voltage rises, and with inept handling, an expensive Pentium II could turn out to be a Celeron “Covington”, if such microcircuits failed.By the way, they warmed up decently on Pentium II processors based on the “Klamath” core so cooling was very important as well. The multiplier in 99% of Pentium II processors was locked (very early production ones were unlocked and Engineering Samples of course), so overclocking was performed by raising the FSB frequency, this being dependent always on the cache and TAG chips installed in that particular processor.

 

A simple example. In Costa Rica, where Intel has an advanced advanced processor assembly/test factory, which simultaneously assembled high-frequency models with 450 and 300 megahertz. The cartridge and core for these processors are identical (and the multiplier was the same 4.5x as well 66×4.5 for the 300 and 100×4.5 for the 450). The difference was only in the installed cache memory with different speed rating in nanoseconds. Sometimes on the assembly line there was only a fast cache memory capable of operating at a frequency of 225 MHz, intended for models of processors with 450 MHz. In this case, it was also installed on the model with a frequency of 300 MHz, as a result of which they overclocked perfectly.

Genesys B52 MMX CPU

The history of the Italian processor began in the city of Monopoli, in the province of Bari in Italy. In 1998, Italian Marcello Console founded Genesys, which initially employed 10 people. The main idea of the Genesys business was the production of modified Intel Pentium II processors based on the “Deschutes” core, at a much lower price than the Pentium II ones of similar clock speed. Plus a warranty period extended to 3 years and productivity increased by 5% or more. It turns out to be a solid Attraction of Generosity!

Genesys had registered its own domain www.b52mmx.com and is getting ready to implement their processors in ready-made system units. Unfortunately, nothing is known about the manufacturing process, it remains a mystery to this day. There is not so much information on these processors, but let’s try to figure out what these processors were.

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