Archive for the 'Boards and Systems' Category

March 26th, 2022 ~ by admin

The DEC/Compaq Turbo Laser 6 AlphaServer KN7CH Processor

AlphaServer GS60 and GS140

The DEC TurboLaser 8200/8400 was a series of high end Windows NT compatible servers/workstations introduced in 1995.  After DEC was sold to Compaq (in 1998) the 8200/8400 were upgraded from the EV5/EV56 (21164/21164A) to the 21264/21264A (EV6/EV67).  Compaq wasn’t as bold with code names it seems so instead of being referred to as the TurboLaser they were simply called the TL6.  The machines themselves were also renamed from the 8200 to the GS60 and the higher end 8400 to the GS140.  GS referring to ‘Global Solution’ to reflect Compaq’s international marketing of the computers.  The GS60 was the lower end rackmount model supporting up to 6 CPUs and 12GB of RAM and the GS140 full cabinet model supporting up to 14 CPU and 28GB of RAM.  Both could be configured with either 21264 525MHz CPUs with 4MB of B-cache each or 700MHz 21264A CPUs with 8MB of B-cache each.  The 21264A added support for writeback cache, as well as its faster speeds and some new instruction set extensions.  Initially availability of these systems was in late November of 1999, coinciding with the release of the 21264A CPUs.  By the time of their release Alpha support for Windows NT was lagging, so most if not all systems were sold with Tru64 UNIX or OpenVMS OS.

The GS60/140 were large cases similar to a rackmount system but self contained.  The processor modules for them contained a pair of CPUs, the cache for the CPUs and the entire chipset.  They connected to the main computer with a very large connector that provided power (48VDC) as well as all the Memory/IO and clock signaling.  This was referred to as the TLSB (TurboLaser System Bus).   The fastest of these was the KN7CH (also known as the E2067-DA) which had dual 700MHz 21264A processors with 8MB of Cache each.

DEC KN7CH 6/700 Processor Board

This processor board is quite interesting, its a rather early board (PLDs are dated March of 2000) and the pair of Samsung 21264A processors are dated 9944, these are some of the very first production 21264As.  Also of interest is that these Samsung CPUs are 733MHz models (KP21264A-733UCN).  The 21264A was to be made in 600, 650, 667, 700, 733, and 750MHz versions, though I have only actually seen 667 and 733MHz versions.  Making only 2 speed grades of the processor would greatly simplify testing and logistics, and with a rather limited customer base, there wasn’t a clear marketing need to make so many different speeds, these were not CPUs that were generally available outside of OEM use.  These servers were also designed to be high reliability systems, running a 733MHz rated CPU at 700MHz would increase reliability by decreasing heat related wear and tear.

Build Sheet for a 8-Node GS140 with Eight 6 CPU GS140 6/700 Systems. Each with 12GB of RAM. A nice $9 million system

The entry price for the AlphaServer GS60 with 4 GB of memory was $199,990 ($340,000 in 2022). The AlphaServer GS140 system price started at $399,400 ($680,000 in 2022). These were very expensive systems.  One look at the processor board shows what that kind of expense gets you, a whole lot of gold.  Its hard to find another computer system built in 2000 that has 9 gold/ceramic chips on each processor board.  A single dual processor board was $45,000 ($76,000 in 2022USD), and each 4GB of RAM was another $49,000.  One can easily see how such a system could quickly cost several million dollars.  Each of these boards cost as much as a really nice car!  Lets look at what that $45,000 gets you

Top Row (L->R) SWI, Alpha 21264A, SWI – Bottom Row: TDI, TDI, TCC, TDI, TDI

2x KP21264A-733UCN. Each 21264A chip has a separate address and data bus for the B-cache and system operations. The 21264A chip has a 64-Kbyte instruction cache and a 64-Kbyte data cache.  These are made by Samsung on a 0.25u process and dissipate 85Watts at 2.0V.

20x IBM SRAM Cache Memory: 8-Mbyte ECC L2 cache per CPU made using 16x IBM 0418A81QLAA-4 512Kx18 8Mb ECC SRAM chips and 2x 128Kx36 / 2x 256×18 for the TAG RAM

2x DEC 21-47306-01 SWI: Two swizzle (SWI) chips receive data from the 256-bit wide DLSB (the DEC Local Bus) and pass it to one of the CPU chips over the 64-bit wide data interface bus.  These are located on either side of the pair of CPUs.

4x DEC 21-47307-01 TDI: Four TurboLaser Data Interface (TDI) chips receive data from the TLSB (the main system bus that connects all cards in the system) and pass the data over the DLSB to the two SWI chips.  These are the outer 4 chips on each end of the row of 5 gold chips on the bottom.  Each one handles 64-bits of the 256-bit TLSB.

1x DEC 21-47315-01 TCC: The TurboLaser control chip (TCC) takes commands from both CPUs and issues them to the TLSB. It also controls all data movements through the TDI and SWI chips. This is the center chip between the pairs of TDI chips.

2x AMD AM29F080DB-90EC: 5V 8Mbit Flash for the system firmware

4x Galaxy Power DC-DC Converters.  These regulate down the 48VDC supplied by the systems redundant power supplies to the voltages needed for the board.  There is a pair of 2.2V 7A converters for the CPUs, and a 7A 3.3V converter for all the I/O.  There also is a smaller 2A converter of unknown voltage (likely 5V).

Pair of Samsung KP21264A-733 Processors surrounded by cache chips

The TurboLaser line was replaced in 2002 by the WildFire servers (GS80, GS160 and GS320) which upgraded the CPU support to 32 21264Cs with 256GB of RAM.  Unfortunately by this time Compaq had merged with HP and the combined server line was a bit cluttered, having Alpha, PA-RISC, Itanium and Xeon based systems.  The Wildfire and its Marvel follow on were the end of the road for the Alpha.  Unfortunately the same thing happened with the PA-RISC and Itanium (ok maybe not so unfortunately with Itanic) as well.  The days of boards full of golden RISC are past, replaced by BGAs with enormous heatsinks.

Posted in:
Boards and Systems

February 11th, 2022 ~ by admin

How do you test a S3 GPU? With an HP 93000

GammaChrome XM18 – Engineering Sample

Recently I got in some very nice S3 GammaChrome GPUs.  The GammaChrome was S3 (owned by VIAs) follow on to the DeltaChrome and included support for such things at PCI-E.  The S18 (Code name Brooklyn) supported speeds of up to 500MHz and was made on a 130nm process by TSMC.  S3 also made a mobile version of the S18 called the XM18 (Code name Metro MPM) in 64MB and 32MB versions.  Clock speed on these was around 350MHz (memory on the samples I have is 350 so core should be similar).  The XM18 was packaged on a MPM (Multi Package Module) with 2 RAM chips and the GPU mounted on a small chip size BGA with around 800 balls.  This is very similar to how ATI packaged some of their mobile GPUs (like the Mobility Radeon 7500 and 9600).

HP 93000 (from HP Brochure)

So how do you test one of the XM18 Engineering Samples? Or any large scale chip for

86C813 ES Gamma Chrome XM18 ULP MPM64

that matter?  With Automated Test Equipment.  ATE systems are designed to rapidly test various chips to verify their design/performance before they go into full production (or to test samples of production ones).  The HP/Agilent 93000 (spunoff as Verigy in 2007 and acquired by Advantest Corporation in 2011) was introduced in 1999 to handle such testing, and at the time was rather revolutionary.  Previously most test systems used a simple test head that would mount the chip to be tested, with all the processing and customizations being contained in the main test machine.  This worked fine for a single design, but to test multiple chips got pretty expensive.  HP moved the testing to the test head directly, interfacing to the target chip via a large PCB.  This way changing chips only required updating the test program, and changing out the PCB.  Design changes required reworking a single PCB, rather then the entire test machine.

HP 93000 Test Head – Notice the 16 groups of pins (some covers and some mangled in this old sale photo)

The 93000 was the first ATE that achieved (on its low end (200Mbps) a cost of $1000/pin tested, and on the high end, test speeds of up to 1250Mbps (for the P1000 version, at a cost of $6-7000 per pin).  The XM18 has around 800 pins, half are probably power/ground so 400 some odd testable pins, in a mid range HP 93000 and you see these systems were not inexpensive. Well over a million dollars for a midrange system.

GammaChrome XM18 – Metro MPM Test Board

To use such a system the chip to be tested would be mounted on the test board, usually with a BGA socket.  This board breaks out all the various connections of the chip to 16 sets of contacts, which the probe head of the HP 93000 made contact with using spring loaded contacts.  The board is then clamped down and tests are run.

Connection List

These boards are very very large, each one is 17x23inches (43x58cm) and 5mm thick.  They weigh about 7lbs (3.1kg) as well.  They got used a lot and need to be rather robust and durable.  You can see the boards are marked with tables of all the connections, and where they are brought out to.  Useful information about what supporting equipment is need (sockets and stiffeners etc) is marked on the board as well.

Back of board. Notice all the capacitors, a crystal, and a series of 5VDC reed relays (the red devices)

These boards appear to be a ‘static’ type item, but they do require adjustment, notice the markings that say not to use this board, it needs recalibrated.  Looking closely at the board you can see capacitors have been removed/replaced, and many of the capacitors have felt tip marker markings on them.  Keeping the capacitance and inductances at their proper values 9and matched, considering the long trace lengths) would be a very important thing.

S3/VIA Matrix Test Board. The Matrix was the code name for the GammaChrome S14/S19

These test boards are from 2006, the 93000 systems are still being used today in upgraded form (now called the V93000) to test SoCs and other chips.  As chips have gotten more and more complex, faster, and with larger pin outs, test equipment continues to grow ins peed, and cost as well, but is an essential part to the process of designing, producing and supporting a successful GPU or CPU.

Tags:
, , ,

Posted in:
Boards and Systems

October 22nd, 2021 ~ by admin

The IBM 4020 Military Computer – Tracking Missiles with 6-bit Bytes

IBM 4020 Q-Pacs – 1960’s

Back in the late 1950’s two things were happening (ok more then 2 but 2 relevant to todays discussion) the military was looking to replace the new but now already out of date tube based SAGE and AN/FSQ-7 Strategic Air Command (SAC) computers, and multiple bits of data were beginning to be called bytes.  The SAC was in charge of all of the US’s Strategic bombers, ICBMs, and detecting/tracking the threats of bombers/ICBMs from the USSR.  The older tube based SAGE computer was designed for relaying, consolidating, and displaying data from Early Warning RADARs across North America to paint a situation picture of what was going on.  It worked fine, for bombers, but the late 1950’s also brought about ICBMs, and ICBMs are much much faster then mere bombers.  The SAGE, and the AN/FSQ-7 lacked the processing speed to keep up with the changing data from a RADAR track of an ICBM so something faster was needed.

Each module weighs around 90 grams

IBM developed and proposed the AN/FSQ-31 (and the FSQ-7A which got renamed the FSQ-32) which were based on the newly developed IBM 4020 military computer.  The IBM 4020 was completely transistor based and designed for reliability and speed.  Marketing materials of the time refer to its ‘resistance to the effects of nuclear blast,’ clearly this was the 1950’s.  At the heart of the 4020 designs was the Q-Pac. These were pluggable, ceramic encapsulated circuit packages. The majority of all logic requirements can be met
by seven basic types of Q-Pacs, each containing from one to four circuits. The use of transistors, diodes, and resistors/caps on each Q-Pac served as what TTL/RTL of the 1960’s/1970’s formed, discrete logic elements, albeit simple ones. In the 4020 the computer was divided into modules (racks) which each contained 16 drawers. Each drawer could hold 96 individual Q-Pac (or 48 double Q-pacs).  That’s 1536 logic elements per module, and the 4020 had 8 modules, resulting in around 12,288 Q-Pacs.  It appears each Q-pac could support 6 discrete transistors, so the 4020’s basic data path (not counting memory, I/O or storage subsystems would max out at 73k transistors.  Obviously there would not be a system that was ALL transistors but this gives us an idea of the scale of the computer. This is around what the Motorola 68000 CPU had or a Intel 80186.  The typical 4020 (again not counting the peripherals) was water cooled, used 13kw of power and took a good 85 sq ft of floor space.

Five simple transistors in the one on the left, and a pair of diodes on the right.

The 4020 was a 48-bit word length (pus 2 parity bits) computer and was capable of around 400,000 Instructions per second with a 2.5microsecond cycle time (6.25MHz).  It supported 128kwords of drum storage (remember 48 bit words, so this is about 6Mbit.  The 4020 also supported byte processing, using the 48-bit word as 8 6-bit sections which IBM called bytes.  This is one of the first official commercial usages of the term ‘byte’ for a chunk of data.  We think of bytes as 8-bits but thats only a standard thats been around the last 30 years or so.  Back in the 1950’s it was the wild west of data naming.  It was common to use 6-bits for BCD (Binary coded Decimal) and 6-bits to represent characters, so a 6-bit byte was only natural for IBM to use.  This eventually gave way to the 8-bit bytes we all know and love by the late 1960’s, though some processors even in the 1970’s used 12-bit words (Intersil 6100 and some PICs) and other oddities (14 bits from the PIC16).

AN/FSQ-31

The process of integrating the 4020’s into SAC facilities took longer then expected, not being completed until 1968, by which time they were of course outdated again.  By 1975 most of them had been replaced by newer Honeywell systems.  Interestingly, the 4020’s tube driven predecessor lasted in some bases until the early 1980’s.

It wouldn’t surprise me if, even after 60+ years, these Q-Pac modules still worked, after all, that was their intended design, to be rugged and reliable.

The Q-Pacs are in a lot of ways an early predecessor the IC’s of today, a single module containing various logic elements, while not on a silicon die, they were ‘built’ by hand, on a ceramic substrate.

 

 

 

Posted in:
Boards and Systems

July 15th, 2021 ~ by admin

The Intel 8086 Gets ICE’d

A while back I received this rather unusual board. Made in 1979 it was clearly a prototype, being a completely handmade wire wrapped board made ona standard Intel MULTIBUS breadboard from 1974. No CPU was present, but a 3M TEXTOOL socket for a CPU is. The paper sticker on the board reads ICE-86/86A/88/88A TEST FIXTURE K95 and DSO TEST ENGINEERING.

ICE-86/86A/88/88A Prototype Test Board

The ICE-86 (and ICE-86A/ICE-88/88A) were all MULTIBUS In circuit Emulators Intel made for the iAPX86 processors in 1979-1985 or so. These were 3 board sets, with a emulator pod (containing a 808x processor) meant for developing and testing x86 software and hardware designs. The boards would plug into a Intel MDS or MDS2 system (or Intel Intellec) and with supporting software, formed the basic of much of the original x86 hardware/software design of the era.  I assumed this board was part of that set, but alas, while researching it I got ICE’d.

Remember wire wrapping? And using all one color for everything?

The ICE-8x systems are based on a Intel 8080A processor, so I checked the pinout on the socket on the prototype, VCC/GND did not match that of an 8080A CPU, it DID match that of a 8086.  Furthermore the clock generator on the board is a P8284, thats the clock generator for the 8086/88 processor, taking the 15MHz crystal input, and outputting a 5MHz clock. The 8080A processor of the ICE-86 emulator system uses a 8224 clock generator (which is a divide by 9 clock generator, usually running on a 9-10MHz or 18-19MHz Crystal).  To make matters more interesting I also have a couple later board (1982 production) which are clearly production (likely limited as the part numbers are still hand written) of the prototype.  They are labeled as ICE-86 TEST – 1981.

Production version of the ICE-86 TEST made in early 1982. Curiously this is a MULTIBUS board but about an inch (2.5cm) taller than standard. This was probably not meant to remain in a host system for long.

The prototype has a switch on it labeled ‘ICE’ for switching the board from 8086 mode to 8088 mode, while the production board lacks such a switch (its designed solely for 8086 processors).   The prototype has a pair of D3604A 4k (512×8) PROMs, the production version is running a pair of 3628A 8k versions,m which were not available when the prototype was made.  So what then would the purpose of such a board labeled ICE, that well, isn’t an ICE?

These board’s were designed for testing ICE emulators, and eventually giving end users the ability to test their software on a known working 8086/88 system.  Generally when using an emulator, you would plug the probe into the processor socket on the target system you are developing and the emulator system allows you to set breakpoints, check register values, memory, etc.  These test boards would allow you to develop at least basic software WITHOUT having a target system of your own, as well as to be able to offer an in system test of the entire ICE emulation.  The production boards being labeled ‘ICE 86 TEST’ seem to be just this, how to ensure the proper function of the by then, thousands of ICE-86/88 board sets now in use.  There was very likely a separate board for testing the ICE-88/A systems as well.  Plug the tester into a MULTIBUS slot on the host system, plug the probe cable into the ZIF socket, and run the testing software.  The ROM’s on the proto board are labeled ‘STIPOL’ which is cryptic at best, but onc of their purposes would likely to be to provide STImulus of somesort to the ICE emulator being tested.

The test boards would also give developers either peace of mind or headaches, when designing for the x86, is the problem the emulator not working? or is their a bug in my design?  Now I need to find boards from an actual ICE-86 system.

Tags:
, ,

Posted in:
Boards and Systems

June 27th, 2021 ~ by admin

Navy Hydrophone Noise Canceller: Weitek 3332 Floating Point Based DSP

Navy 55910 ASSY 0120811 Eight Channel DSP – Serial #1

I got these boards some time ago, hoping to be able to figure out more about them but alas, information is very sparse, but they are such good looing boards, with impressive technology for the day, I had to post them

These boards came out of a US Navy system labeled “Hydrophone Noise Canceller”  which seemed to be part of SONAR test system at a University.  These date from the late 1980’s to the early 1990’s. The system was comprised of 16 boards, 12 8 Channel DSP board, a control board, and 3 Ethernet Boards,  Each of these boards is a very heavy 4 layer PCB, with pretty much everything socketed.

The DSP Boards are based on the Weitek 3332 FPU. These are full 32-bit Floating point datapaths (MULT/DIV/ADD/SUB + Registers) and made on a CMOS process.  They operate on a 100ns (10MHz) clock.  THese are the higher end version of the 3132, they have a full 3 busses versus the single bus of the 3132.  These 3 busses add a lot to the pincount (168 vs 144) and thus cost but make designing a system more flexible, no bus sharing to worry about.  The 3332 was designed specifically to support high speed DSP and graphics processing.  It performed the ‘core’ of a DSP, allowing the user to build around it and make essentially a custom DSP for their application (unlike the purpose built TI TMS320 series of DSPs also available at them time) On the board they are backed by 4 Cypress CY7C128 2K SRAM per processor (8K total).  There is no clock crystal on the board itself, which is typical of a system like this.  To ensure everything stays in synch, the clock would be provided by the control board and distributed to each of the boards on the bus.

Navy 55910 ASSY 0125321 Controller A80386DX-25 (20MHz) Serial #2

The Control Board runs an Intel A80386DX processor.  On this particular board its a 25MHz chip, but note the crystal next to it is an 80MHz crystal.  A 386 internally divides the clock by 2, so the 80MHz clock is most like divided by 2 externally resulting in a 40MHz input to the 80386, and a 20MHz CPU clock.  I had another controller board with a 20MHz 80386 so they probably just used what ever they had available.  This is Serial # 2 afterall.  The 386 is supported by 4 27C256 EPROMs and 8 32K (CY7C198) SRAM chips, giving it 256K of SRAM.  In addition is 12 8k (CY7C185) 8K SRAM chips each with there own Pipeline Register.

A typical 386 system would have several MB of RAM, but this system is set up for real time data processing, as a DSP system, so the only data that needs to be in RAM is the control program itself, so 256K of system RAM is a great plenty.  Additional RAM is likely used solely for buffering data from the Hydrophones.

It would be interesting to know what this board was used for in more detail, but even if that never happens its an interesting board for its time.  Clearly a vast amount of effort went into designing and building the system.

 

Tags:
,

Posted in:
Boards and Systems

May 17th, 2021 ~ by admin

First & Last AMD Socket A Athlons – Thunderbird vs. Barton – Part 2

Continuing our exploration of the evolution of the Socket A architecture.  See Part 1 here

Test Stand

For tests of all processors with a final frequency of 1 GHz, several processor / RAM operating modes were selected: 100/100, 100/133, 133/133, 133/166 MHz, priority was given to modes with the highest RAM frequency.

The main components of the system:

CPUs:

AMD Athlon XP-М, (10x 100 и 7.5x 133) 1000 MHz, Barton
AMD Athlon (B), (10x 100) 1000 MHz, Thunderbird
AMD Athlon (C), (7.5x 133) 1000 MHz, Thunderbird

Motherboards:

  • ASUS A7V, chipset VIA Apollo KT133
  • ABIT KR7A, chipset VIA KT266A
  • EPOX EP-8K3A, chipset VIA KT333
  • EPOX EP-8K9A7I, chipset VIA KT400A
  • EPOX EP-8RDA3I, chipset Nvidia NForce 2 Ultra 400

Memory:

  • OCZ PC3200 EL Platinum Edition (OCZ4001024ELDCPE-K), 512 Мб х2 (PC3200) CL=2

Videocard

  • Gainward – GeForce 6800 Ultra AGP 256 Mb (Forceware 81.85).

Testing was carried out in Windows XP Sp3 using the following software:
• Super Pi mod. 1.5XS (1M task)
• PiFast v.4.1
• WinRAR x86 v. 5.40
• Cinebench 2003
• 3Dmark2001SE Pro b330
• 3DMark 2003 v.3.6.1
• AIDA64 5.50.3600
• PCMark 2004 v.1.30
• Max Payne
• Far Cry
• DOOM III

Tests

When testing all platforms, I used the same Windows XP SP3 distribution with the same list of running services and settings. Gainward GeForce 6800 Ultra AGP 256 MB together with Kingston V300 60 GB SSD remained unchanged companions throughout the tests. Windows XP SP3 was installed from scratch for each platform. All VIA chipsets used VIA Hyperion 4-in-1 Driver version 4.51. For the video card – Forceware 81.85. All unnecessary services were disabled, the system was tuned to high performance mode.

Read More »

Posted in:
Boards and Systems

May 14th, 2021 ~ by admin

First & Last AMD Socket A Athlons – Thunderbird vs. Barton – Part 1

Introduction

The AMD Socket 462 or Socket A, was a rather interesting and long-lasting CPU Socket. The first models of Socket 462 processors appeared in the summer of 2000, they were just the first representatives of the AMD Athlon “Thunderbird” in a ceramic case with a clock frequency of 600 MHz, and with 256 KB of L2 cache , an effective system bus frequency of 200 MHz, with MMX support instructions and their own 3DNow !, of course, there was no question of any SSE in those days. Produced ” Thunderbirds” at 180 nm. tech process, the operating voltage was set in the range of 1.70-1.75 volts, and the maximum heat dissipation was 72 watts for the older model 1400 MHz versions.  These replaced the old Slot A cartridge based Thunderbirds, made possible by the L2 cache being moved on die instead of off die (in similar fashion to Intel’s Coppermine Pentium IIIs moving to S370 from Slot 1).

Thunderbird die exposed

The last representative that was designed for Socket 462 was AMD Athlon XP+ using the “Barton” core, released in early 2003, which retained its position throughout 2004. With “Barton” the ceramic case is a thing of the past, being replaced by a Organic PGA package. The process has decreased to 130 nm, the L2 cache capacity has doubled, the system bus frequency has doubled, and the clock speeds have exceeded 2.2 GHz.

The fastest model had a real frequency of 2200 MHz and a performance rating of 3200+, the operating voltage was 1.65 V, and the TDP was 77 W with a 400FSB.  These was also another AXDA3200 with a 333 FSB, this actually clocked slightly faster as 2.333GHz, but was given the same PR rating due to its slightly slower FSB. The processor acquired the first generation SSE instructions, and the motherboards created for it in that day now added support for dual-channel operation of the RAM. If we add here that the first motherboards based on Socket 462 worked with SDRAM memory, and the subsequent ones with DDR-SDRAM, then according to a number of indicators there is a twofold increase in the main characteristics of the platform within the framework of one socket.

Such a funny comparison reminded me of today, where from the time the first generation of AMD Ryzen processors appeared in 2017, until the last (fourth gen), which debuted at the very end of last year (2020), all processors also had one AM4 socket. Ryzen performance gains across all four generations are clearly exemplified by the following slides:

AMD hasn’t had much of a problem with processor support before, although AMD has officially announced that Ryzen 5000 series desktop will only be supported on boards with 400 and 500 series chipsets. Therefore, on motherboards released for the first generation Ryzen, it will not work to use the latest generation processors in an official way. Although there is information on the network that there are cases of using Ryzen 5000 series processors on motherboards with the older X370 chipset, but the official position of AMD has already been announced above.

In the wake of such analogies, I thought, why not compare the first and the last Athlons for Socket 462 on several motherboards at the same clock frequency, with the same system configuration? You will find out the result of what came out of this by reading this article to the end.

Continuation of the Idea

The essence of the idea is simple – take the first AMD Athlon based on the “Thunderbird” core with a 200 and 266 MHz system bus and a clock speed of 1 GHz and an AMD Athlon XP representative on the “Barton” core with a similar round frequency of one GHz, and compare them with each other to find out how much the first generation loses to the last one. During the existence of Socket 462, several generations of processors with different cores have changed on it: Thunderbird – Palomino – Thoroughbred – Thorton – Barton.  This will be an interesting test of raw architecture improvements of the core. all other things being as equal as they can be.

Read More »

Posted in:
Boards and Systems

February 25th, 2021 ~ by admin

The 486 CPU Era – The Birth of Overclocking. – Part 2

In Part 1 of The 486 CPU Era – The Birth of Overclocking, we covered some of the basics of the 486 era and where it came from, as well as the various brands/types of 486s of the era (many of which we will test and attempt to overclock.  In Part 2 we will discuss the hardware selection and rational, testing environment and benchmarks! (and a healthy dose of Overclocking with some perhaps surprising results)

Choosing a Motherboard

Socket 5, GIGABYTE GA586AM, UM8891BF / UM8892BF chipset – Good but not good enough

Choosing a motherboard for the 80486 platform is not easy. There are several criteria or approaches for the implementation of such projects. 1. Consider whether you need PCI slots? 2. The need for VLB slot(s) 3. The need for everything on one board.

Since I set myself the task of assembling the most productive Socket 3 system, the presence of ISA and VLB slots was a secondary matter for me, PCI slots were a priority due to their speed characteristics. The fastest chipset was required from the motherboard – this is the UMC 8886/8881. Revisions of this chipset were later used in Socket 5 Pentium motherboards that supported FSB 60/66 MHz and higher. The board must have 4 slots for RAM with support for EDO RAM, the minimum total size is 128 MB (4x 32 MB).

The total size of the L2 cache should be equal to 1 MB, so the motherboard should contain 8 sockets for such microcircuits.

Due to the use of different processors with different input voltages, the board must support a choice of voltages from 3.3 V to 5 V in small steps, in order to be able to “smooth” overclocking. Accordingly, the overclocking capability on the bus from 33 to 50 MHz and higher should be implemented. So which board do we end up with?

Read More »

Posted in:
Boards and Systems

February 21st, 2021 ~ by admin

The 486 CPU Era – The Birth of Overclocking. – Part 1

Introduction

486 CPU Era – the birth of Overclocking – this is how I decided to call everything that was in the pre-Pentium era, which I did not find and become familiar with until a couple of months ago.

(Another Article in cooperation with max1024 of Belarus – Edited/Expanded by Me)

If we abstract from the very first Pentiums, which appeared using Socket 4 in two speeds of 60 and 66 MHz, then these processors won popular fame and love in motherboards based on Socket 5 and 7. Such machines could be seen in the early 90s on which while playing C&C, Warcraft and other RTS games. The Sega Mega Drive II and Super Nintendo game consoles competed with expensive computers. Moreover, the consoles were far ahead in popularity (and to be honest, the graphics and game play were better) and I got used to the joystick much earlier than to the mouse and keyboard.

The question arises, what was there before all these Pentiums? And the answer, if you dig deeper, can discourage or even confuse any inveterate computer enthusiast, since the cultural layer of “hardware” from the very first processor belonging to the x86 architecture to the first representatives of the superscalar architecture is much larger than from the Pentium 4 to the freshly released Intel Core i9-11900K, which belongs to the Rocket Lake family of 11th generation Intel Core processors. It is not so easy to digest this entire historical layer, so I have outlined the framework for myself.

To simplify the chosen concept, I decided that the platform should in any case support the PCI interface, since it is, firstly, relatively fashionable and “modern” and, secondly, gives more room for my experiments with the accumulated PCI expansion cards. I did not impose other, special requirements on the test platform, except that according to the established tradition, it should be the most powerful and fastest set that is possible to assemble.

Here I think some of the readers of this article the “True oldies” will say: “what is this nonsense, where is the ISA, VLB and 8-bit only?”, But everything has its time, we will gradually dive into the depths of the prehistoric hardware sea, otherwise decompression cannot be avoided. [Editor’s note, I grew up on an 8-bit 8088 and of course connected the PC Speaker to a 100 Watt Stereo Amp, the loudest 8-bit beeps ever]

typical VLB videocard – V7 Mirage P64 on S3 Vision 864, 2 Mb (before they hid all the good stuff with a heatsink)

So, let’s play from the presence of the PCI bus, which appeared just during the heyday of 4th generation processors, “fours” or simply – four hundred and eighty-sixths, which first appeared back in 1989 or today it is 32 years ago. “Almost like yesterday” the oldies will say, “We were not born yet,” the rest will answer, although this is not the point.

The previous generation of 386 processors was content to exchange data with peripheral devices more often at the “width” of 8 and 16 bits, although the entire generation of processors belongs to the first microprocessor architecture supporting 32 bits, but despite this, motherboards designed for them had no  32-bit PCI bus. Although this could not have happened historically, since the specification is new, in relation to the previous buses, it (PCI) was first implemented in 1992. This means that the whole choice comes down to the whole variety of 486 processors, and there was enough variety in those years, not that today there is a choice between “red” and “blue”.

Read More »

Posted in:
Boards and Systems

September 29th, 2020 ~ by admin

Aircraft Instrumentation, Bitchin’ Betty and an 80C86 CPU

F-15 with P4 Instrumentation Pod – Looks like a missile under the wing, with blue and red stripe.

Quite the combination I know, but of course all related.  Last week I got some boards in that were quite interesting.  They were all fairly early serial numbered, from the 1980s and military in design.  Now one thing about anything military is identifying it is pretty hard to do, especially when it hails from an era before the Internet.  Many records from the 1980s have made it online, but OCR and transcription errors abound, a single wrong digit can turn an item made for a A-4 Skyhawk into a new blade from a lawnmower or a shiny new Navy mess tray.

Thankfully these boards all had a CAGE code which the US uses to identify each and every supplier.  In this case that code was 94987 which is Cubic Defense.  Cubic didn’t make lawnmower blades or mess trays but they did make a lot of instrumentation systems for aircraft (and they continue to do so).

F-16 with blue training pod under its left wing)

It turns out that training fighter pilots is best done without having to use live weapons, for obvious reasons, but in all other aspects should remain as true to lifer as possible, and then be able to be analyzed after that fact in order to learn from mistakes, and see who gets bragging rights for pulling the most G’s.  This means that the aircraft has to send and receive data as it would in combat, threat warnings have to go off when targeted, missiles have to be ‘launched (while being captive) at the appropriate times, and every aspect of the flight must be recorded, speed, roll rates, altitude, etc.

Cubic made pods, that attached to one of a fighters weapon hardpoints (typically the outermost) that did exactly that.  These pods interface with the aircraft’s flight systems (using the standard 1553 bus) as well as with ground based systems on the training range, forming a complete picture of what is going on between all the aircraft taking part.  These particular boards are from Cubic’s second generation digital pods, the P4 series (the first gen was, the P3). Specifically the P4A series.  Each pod contained a vast amount of sensors, antennas and instrumentation to monitor and record what was happening, as well determine if a missile as ‘launched’ to or from the fighter.

Cubic 185200-1 with Harris ID80C86 – The brains of the AN/ASQ-T25 P4AM Training Pod

At their heart was a Harris or Intel 80C86 processor, (Harris actually did the CMOS conversion on the 8086).  This is one of the earliest applications of the CMOS 8086.  In this case the 80C86 is running off of the normal 8284A clock generator and a 13.5MHz crystal. This results in a processor frequency of 4.5MHz, a bit under its 5MHz rating.  This is pretty typical of military applications, it generates less heat, draws less power, and gives more margins.  This particular board has a industrial spec CPU, later production versions had a full military qualified part (this board was a prototype).

Read More »