Archive for the 'CPU of the Day' Category

July 3rd, 2018 ~ by admin

CPU of the Day: The Intel Everest Series

Mt. Everest – Tallest on Earth

Mt. Everest is the tallest mountain here on Earth, the pinnacle of climbing challenges.  There is no going higher then Mt. Everest.  At Intel the pseudo-unofficial codename for the absolute fastest speed bin of a particular processor is…Everest.  Everest processors are the fastest an architecture will so reliably.  Sometimes these processors end up an normal products, available for consumers to purchase.  The first good example of this is the Core 2 Extreme QX9775 Yorkfield core (Core Architecture).  They were a quad-core processor running at 3.2GHz, fast but not mind blazingly so.  The Xeon equivalent was the X5492 (Harpertown) 4-core at 3.4GHz.

Xeon X5698 – Westmere – 4.4GHz – Mid 2010

The next well know Everest was a chip based on the Westmere (shrink of Nehalem) architecture.  The Westmere Everest became known as the Xeon X5698, and was available for OEMs only, in fact it was a special order processor made with one particular type of client in mind. These were to be used for High Frequency Stock traders, and other such high speed transactional processing, where the ability to complete trades as fast, and reliability as possible is the entire nature of the business.  This means that single thread performance is far more important then having multiple core, and as such, the X5698 uses a 6-core die with only 2 cores active, but retaining access to the entire 12MB of L3 cache.  Clock speed was fixed at 4.4GHz, the cores did not reduce frequency as processing demands changed, as this would introduce uncertainty in how fast it would complete a given task. Doing task ‘X’ should take a predictable amount of time and not depend on what speed the processor chose to run at.  The next fastest Westmere processor was the X5690, which was a 6-core (all cores enabled) running at 3.46GHz (the same chip essentially as the Core i7 990X).  The X5698 was nearly 1GHz faster.  The X5690 cost around $1800, where as the X5698 cost around $20,000 EACH (based on costs OEMs charged to add a 2nd one so they may have marked it up some).  The impressive thing is that these chips would go faster.  Intel sampled 4.66GHz versions and Supermicro built systems using X5698’s overclocked to 4.8GHz.  All this back in 2011.

4.4GHz Jaketown (Sandy Bridge) Everest Sample 2010-2011

Intel’s next architecture was known as Sandy Bridge.  Sandy Bridge topped at at 3.5GHz (6-cores) for the Core i7 Extreme 3970X and 3.6GHz for the 4-core i7-3820 and similar Xeon E5-1620.  Intel demo’d an air cooled Sandy Bridge running on stage for a presentation at 4.9GHz, so the core certainly had some room to spare.  There is no documentation (that I could find) that Intel actually released anything faster then 3.6GHz, at least that I could find, but evidence suggests that they at least were thinking about it.  The picture is a Sandy Bridge Xeon in LGA2011 marked JKT EVEREST SS 4.4GHZ INTERNAL USE ONLY. JKT is short for Jaketown, Intel’s codename for the 32nm Xeon E5-2600 series.  That gives a very good idea what this processor was to be.  SS is likely to be a Single Socket (as often at those speeds getting dual systems working can be tricky).  Sandy was certainly capable of hitting 4.4GHz, with 4-core, and even air cooling, so perhaps these were samples for a limited OEM run, much like the previous Westmere X5698 processors.

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April 11th, 2018 ~ by admin

PowerPC Processor for TESS Planet Hunter – Updated

TESS Orbiter – Freescale (now NXP) 2010  PowerPC e500

UPDATE: I received a note from a NASA engineer that the final flight DHU was made by SEAKR Engineering rather then Space Micro.  It turns out MIT pursued 2 different DHU systems in the design of TESS.  The Space Micro IPC 7000 was referred to as the DHU and a system by SEAKR (the Athena-3) was selected as the ADHU (Alternate Data Handling Unit).  Apparently MIT wasn’t sure which would be best so essentially characterized both (and most documentation from early on shows the Space Micro system).  In the end however, the SEAKR Athena-3 Single Board computer was selected.

If all goes well, in a few days the NASA TESS (Transiting Exoplanet Survey Satellite) will be launched on a SpaceX Falcon 9 rocket to startits mission to survey a large portion of the sky for possibly Earth-like planets.  TESS’s finds will make great candidates for further study by either Hubble, or JWST (when it finally launches).  While TESS can see transiting planets (the dimming of a star as an exoplanet passes in front of it) it cannot determine much about its composition, or the composition of its atmosphere.  However, having a list of exoplanets to further check out, especially Earth-sized ones, it’s a big help.  TESS was created as part of the NASA Medium Class Explorers Program (MIDEX) which is for mission up to around $200 Million total cost to NASA (not including launch).  TESS itself cost about $75 million (developed in large part by MIT and built by Orbital-ATK on their LEOStar-2 Platform) and the launch services contract was $87 Million with the remainder taken by operations and contingency funding.

Space Micro Proton 400k with Freescale 2020 processor

That makes this one of the least expensive NASA missions, but one that has engendered much more public interest then its cost suggests.  Finding alien worlds captivates people hearts and minds.  So what is at the heart of the TESS orbiter?  Obviously the premier technology is its 4 cameras that will scan the sky, but the computer that powers these is no less interesting.

The 4 cameras are interfaced to a Data Handling Unit (DHU).  Initially the DHU was to be the Space Micro IPC-7000 computer.  The IPC-7000 consists of a TI TMS320C67xx 32-bit DSP and a pair of Xilinx Virtex-7 FPGAS.  They handle all the pre-processing of the imagery collected by the cameras, making it into a format that is easily transmitted back to earth.  The rest of the spacecraft functions (such as actually sending/storing the data and other space craft house-keeping) is handled by a Space Micro Proton 400k SBC.  The Proton 400k is based on a Freescale 2020 1GHz Dual Core PowerPC processor made on a 0.45u process..  Each PowerPC e500v2 core has a 7-stage pipeline with 32K of I-cache and 32K of D-Cache and shares a single 512K L2 Cache.  The computer also containing a pair of 192GB solid state memory boards for buffering imagery data (data is relayed to Earth only once per orbit, so it needs to store data from around 14 days).

Athena-3 SBC – Powered by a 1.067GHz Freescale P2010 Processor

The final flight version of TESS switched to an ADHU made by SEAKR Engineering.  This uses a very similar setup but a bit less powerful processor.  The heart of the ADHU is the Freescale P2010 e500 processor at 1066MHz with 1GB of DDR2 RAM and 1-4GB of Flash.  This is the single core version of the P2020 used in the initial Proton 400k.  The ADHU also includes a RCC5 triple Xilinx Virtex-5 FPGA board to handle additional camera processing functions (and anything else not handled by the P2010 processor).  Solid state storage is a Gen 3 FMC also by SEAKR, containing 3 boards with a total of 192GB of Flash.  The ADHU handled all of the science, processing the raw camera data into useful science data and handling the sending of data to the 100-125MBit/sec Ka-band transmitter.  It also supplies some star reference information used by the MAU (Master Avionics Unit) computer to provide finer attitude control of the satellite.  The MAU is the LeoStar-2 Satellites main computer, and handles all the mechanics of flying the spacecraft outside of the science work done by the ADHU.

Freescale P2020 Processor

In many ways this is a very advanced processor compared to the RAD750 processors we often see on large scale NASA missions.  The Freescale 2020/2010 is not an inherently radiation hardened design, however both Space Micro and SEAKR  implements many radiation mitigating designs in the system design to compensate for this.  It is not as robust as the RAD750 but it is a $75 million earth satellite with a target mission life of 2-years so it doesn’t need to be. The 2020 processor does give TESS tremendous processing power for a scientific satellite, allowing for a lot of pre-processing of the imagery.  This allows TESS to handle much of the grunt work, and send scientists here on Earth only the very best data, in a format that is the most useful to them.

 

March 24th, 2018 ~ by admin

Making MultiCore: A Slice of Sandy

Intel Sandy Bridge-EP 8-core dies with 6 cores enabled. Note the TOP and BOTTOM markings (click image for large version)

Recently a pair of interesting Intel Engineering Samples came to The CPU Shack.  They are in a LGA2011 package and dated week 33 of 2010.  The part number is CM8062103008562 which makes them some rather early Sandy Bridge-EP samples.  The original Sandy Bridge was demo’d in 2009 and released in early 2011.  So Intel was making the next version, even before the original made it to market.  The ‘EP’ was finally released in late 2011, over a year after these samples were made.  Sandy Bridge-EP brought some enhancements to the architecture, including support for 8-core processors (doubling the original 4).  The layout was also rather different, with the cores and peripherals laid out such that a bi-direction communications ring could handle all inter-chip communication.

Sandy Bridge-EP 8-core die layout. Note the ring around the inside that provides communications between the peripherals on the top and bottom, and the 8-cores. (image originally from pc.watch.impress.co.jp)

Sandy Bridge EP supports 2, 4, 6 and 8 cores but Intel only produced two die versions, one with 4 cores, and one with 8 cores.  A die with 4 cores could be made to work as a dual core or quad, and an 8-core die could conceivably be used to handle any of the core counts.  This greatly simplifies manufacturing.  The less physical versions of a wafer you are making, the better optimized the process can be made.  If a bug or errata is found only 2 mask-sets need updated, rather then one for every core count/cache combination.  This however presents an interesting question..What happens when you disable cores?

That is the purpose of the above samples, testing the effects of disabling a pair of cores on an 8-core die.  Both of the samples are a 6-core processor, but with 2 different cores disabled in each.  One has the ‘TOP’ six cores active, and the other the ‘BOTTOM’ six cores are active.  This may seem redundant but here the physical position of the cores really matters.  With 2 cores disabled this changes the timing in the ring bus around the die, and this may effect performance, so had to be tested.  Timing may have been changed slightly to account for the differences, and it may have been found that disabling 2 on the bottom resulted in different timings then disabling the 2 on the top.

Ideally Intel wants to have the ability to disable ANY combination of cores/cache on the die.  If a core or cache segment is defective, it should not result in the entire die being wasted, so a lot of testing was done to determine how to make the design as adaptable as possible.  Its rare we get to see a part from this testng, but we all get to enjoy its results.

March 15th, 2018 ~ by admin

CPU of the Day: Intel Jayhawk – The Bird that Never Was

Intel Jayhawk Thermal Sample – 80548KZ000000 QBGC TV ES – Made in April 2004 Just 3 weeks before it was canceled

Perhaps fittingly the Jayhawk is not a bird, but rather a term used for guerilla fighters in Kansas during the American Civil War.   It is also the name of a small town in California 150 miles Northeast of Intel’s headquarters in Santa Clara.  It was also the chosen code name for a Processor Intel was working on back in 2003.  In 2003 Intel was working on the Pentium 4 Prescott processor, to be released in 2004 and its Xeon sibling, the Nocona (and related Irwindale),  The Prescott was a 31 stage design made on a 90nm process.  There was hopes it would hit 4+ GHz but in production it never did, though overclockers, with the help of LN2 cooling were able to achieve around 8GHz.  Increasing the length of the pipeline helps allow higher clock speeds, the Northwood core had a 20-stage pipeline so the Prescott was a rather big change.  There is a cost of lengthening the pipe, processors don’t always execute instructions in order, often guessing what will come next to speed up execution.  This is called speculative execution, processors also guess what data is to be needed next, and stick it in cache.  If either of these ‘guesses’ is wrong, the processor needs to flush the pipeline and start over, at a comparatively massive hit in performance.  This is what performance doesn’t always scale very linearly with clock speed.

Intel figured that this wouldn’t be an issue and so the Prescotts successor was to have a 40-50 stage pipeline.   THe hopes were for 5GHz at 90nm and 10GHz at 65nm. The desktop version was known as Tejas, and the server version, Jayhawk.  Initially these were to be made on the 90nm process, same as Prescott, before being transitioned to a 65nm process.  It increased the L1 cache to 24k (some sources say 32k) from the Prescotts 16k.  The Instruction trace cache was still 16k micro-ops, though this could have been increased.  L2 cache would have been 1MB at introduction and 2MB once the processor moved to a 65nm process.  Eight new instructions were to be added called ‘Tejas New Instructions’ or TNI, these later would become part of the SSSE3 instructions released with the Core 2 processor.  It also would bring ‘Azalia’ Intel’s High definition audio codec, DDR2 support, a 1066MHz bus, and PCI-Express support.  It turns out there was a problem….

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January 28th, 2018 ~ by admin

CPU of the Day: Tandem CLX 800 – It Takes 2 To Tango

TANDEM CLX 800 Processor – VLSI CMOS 1u process – 16MHz.

Tandem Computers was established way back in 1974, and was one of the first (if not the first) dedicated fault-tolerant computing companies.  They designed completely custom computers designed for use in high reliability transaction processing environments.  These were used for support of stock exchanges, banks, ATM networks, telephone/communications interchanges, and other areas where a computer failure would result in significant, costly, disruptions to business services.  Tandem was started by James Treybig, formally of HP, and a team he lured away from HP’s 3000 computer line.

Tandem computers are designed to do two things well, fail-over quickly when a failed part is detected.  This means that if a faulty processor or memory element is found, it can be automatically disabled, and processing continues, uninterrupted, on the rest of the system.  The other design element that Tandem perfected was allowing the computer to find and isolate intermittent problems.  If a processor or storage element ceases to work, that is relatively easy to figure out, but if a processor is glitchy, causing errors only occasionally, that can be much harder to find and can result in serious problems for the user.  This is known as ‘Fast Fail’ and today is a pretty standard concept, find the error, catch it, and prevent erroneous data from ever making it back into the database.  Tandem computers were designed from the ground up to be fault tolerant, disks were mirrors, power supplies, busses,

Tandem CLX 600 PCB (click for larger)

processors,all were redundant, but unlike some other systems, components were not kept as ‘hot spares’ sitting idle until something failed.  This kept hardware from being ‘wasted.’ Under normal operation if it was in the system, it was contributing to system performance.  A failed component then would reduce system performance until it was replaced/fixed, but a customer would not be paying for hardware that served them no purpose unless something broke.

To support these goals Tandem designed their own processors and instruction set architecture know as TNS (Tandem NonStop).  The first processors were a 16-bit design call the T/16 (later branded NonStop I) made out of TTL and SRAM chips spanning 2 PCBs.  Performance was around 0.7MIPS in 1976.  They were a stack based design similar to the HP3000 with added registers as well.  T/16 systems supported 2-16 processors. NonStop II, released in 1981, was similar, but supported the occasional 32-bit addressing, increasing accessible memory form 1 to 2MB per CPU and performance to 0.8MIPS.

The 1983 introduction of TXP saw a great performance improvement, up to 2.0 MIPS, but kept the same form factor.  The processor was implemented in TTL, with the addition of many PALs and added much better support for 32-bit addressing.  In 1986 the NonStop VLX was released, which moved to an ECL based processor.  This was a full 32-bit design, running at 12MHz (3MIPS) but still using discrete components and a new bus system as well.  This was to be the high end of the NonStop line, it was fast reliable, and rather large.  The desire for a more economical system to fit the needs of smaller customers led to a first for Tandem…

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December 19th, 2017 ~ by admin

Chip of the Day: TRW MPY-16AJ – Making Multiplication Manageable

TRW MPY16AJ – 1978

In Primary School students are tasked with memorizing their multiplication tables.  Taking the time to manually calculate 6×5 is much slower than simply committing the result to memory.  This allows more complex math to be processed quicker as the students skills develop.  Typically this is limited to numbers up to 12×12, resulting in 144 results to ‘store.’  In computing the same can be done.  A ROM can be used as a lookup table for multiplication.  The problem is it does not scale well.  Handling 4×4-bit multiplication requires a 256×8 ROM (2m+n addresses and m+n outputs). This could be handled by a many ROMs available in the 1970’s.  Anything more than 4-bits though was simply not possible.  This gave rise to the need for multipliers to calculate the result.

TRW MPY16AJ – Large Heatsink affixed to package to dissipate its 5W

This was a problem TRW set out to rectify in 1976.  TRW LSI Products was formed in the 1960’s to commercialize the transistor products that had been developed by Pacific Semiconductors, a division of TRW.  It was James Buie who invented the TTL logic gate in 1961 while working for TRW.  TTL went on to become the logic standard throughout the 1970’s and 80’s.   TRW was involved in aerospace, helping design planes, satellites, and missiles, fields that required processing of signals data, what became known as Digital Signal Processing (DSP).  In the 1980’s processors were designed to handle this, such as the TI TMS320 series, but in the 1970’s it had to be done with discrete components.  DSP systems had several needed blocks, Fast ADCs, ALUs, and multipliers.  TRW invented fast ADCs to handle the inputs, and ALUs were available such as AMDs Am2901 or even the TTL series 74181s.  Multipliers however were not widely available, especially for large bit-widths.

MPY-16 die

TRW’s first multiplier was a custom device to work with their own avionics processing system.  It was made on a Bipolar process, and multiplexed the entire product, using around 40 pins total (the entire product was multiplexed with the operands).  It could handle a multiply in 330ns worst case.  Interestingly yields of the device were considered ‘excellent’ at 3 working devices per wafer (out of 19 per wafer (most likely a 2″ wafer)).  Today, yields like that would be completely unacceptable.

TRW designed the MPY-16AJ as a brute-force 16×16 multiplier.  It was designed on a Bipolar process with around 3600 gates.  It implements a series of AND gates and CARRY-SAVE-ADDERS to implement the multiplication.  There are faster methods, but they come at the cost of complexity and power draw.  As designed the the MPY-16AJ dissipates 5 Watts while handling a signed (2’s complement) multiplication in a worse case 230ns).  They MPY16 was packaged in a large 64-pin package to limit the # of pins that had to be multiplexed.  The lower 16-bits of the product are multiplexed with one of the operands.  This is acceptable as in many applications the upper 16-bits of the product are sufficient accuracy.  The 64-pin package allowed for not less multiplexing, but also a much larger surface for heat dissipation.  A heatsink was also affixed to the package as well.

Micron (Russia) 1802VR5 – MPY16HJ Clone made in 1992

Later versions of the MPY-16 added support for unsigned multiplication as well (the MPY16H) and became the standard for 16-bit multipliers.  Compatible multipliers were made by Analog Devices (ADSP1016, 40-50ns at 150mW) and LOGIC LMU16/216) in CMOS, by Weitek (WTL1516/A/B, 50-100ns at 0.9-1.8W) in NMOS, by Synertek (SY66016 100ns at 1.5W) in HMOS, by AMD (Am29516 38ns at 4W) in ECL, as well as many others.  These were implemented internally with different processes, and different multiplier algorithms but externally they all mimicked the standard TRW MPY16J and served as the basis of many signal processing and high end math computers.  As a testament to their usefulness, the MPY16 was also copied by the USSR as the 1802VR5.  The TRW MPY16 was last made in the mid-1980’s but its clones continued to be made into the 1990’s.  Today its functions can be handled by any DSP, CPU or even coded into a FPGA, but for a time, the MPY16 multiplied the efficiency of many processing systems.

December 7th, 2017 ~ by admin

CPU of the Day: Hitachi HD6801S0PJ – Automotive 6801

Hitachi HD6801S0PJ – 1982 Automotive Spec 6801

The original Motorola MC6801 was released in 1977, built on a 5.1u NMOS process with 35,000 transistors (some sources say 25,000, which may be the ‘active’ transistor sites).  One of the very first customers was General Motors, you can read more about that in last years article on the 6801.  Hitachi was the primary second source for Motorola, primarily to supply the Japanese market, but they also competed with Motorola in the US market as well.  Hitachi released their version of the 6801 in 1980, with full production commencing in 1981.  It was made on a 3-micron NMOS process and was available in both a 1MHz speed (HD6801S0) and 1.25MHz (HD6801S5).  Around this time (1982) Hitachi was also transitioning their part numbering system.  Originally these parts were HD468xx… which was a bit confusing so they dropped the ‘4’.  For several years in the early 1980’s it is not uncommon to find parts with either, or both part numbers on them.

The pictured Hitachi HD6801S0P in interesting for a couple reasons.  The A00 denoted the ROM code for the 2K of onboard ROM.  A00 means that it is unprogrammed.  This would be useful for testing the 6801 with an external EPROM etc.  The ‘J’ on the package denotes that this device is a industrial/automotive spec part with an increased temperature range, in this case -40-85C.  Hitachi date codes are different from other manufacturers but are relatively simple.  The code 2E1 denotes the first week (1) of May (E) in 1982 (2).

Hitachi marked with both old and new part numbers
HD46800DP and HD6800P – dated 3F1 – First week of June 1983

Year* Month** Week
8 – 1978 A – January 1 – Week 1
9 – 1979 B – February 2 – Week 2
0 – 1980 C – March 3 – Week 3
1 – 1981 D – April 4 – Week 4
2 -1982 E – May 5 – Week 5
3 – 1983 F – June
4 – 1984 G – July
5 – 1985 H – August
6 – 1986 J – September
7 – 1987 K – October
8 – 1988 L – November
9 – 1989 M – December

*Years repeat, so 0 is used from 1980 and 1990
** ‘I’ is skipped to avoid confusion with the number ‘1’

What is perhaps more interesting is what came with this CPU when the museum got it.  Its often hard to figure out what a CPU/MCU was used in, or what it was for, its provenance.  This 6801 offers some help.  It came in an original Hitachi box, with a copy of a fax from Hitachi in Japan to the Hitachi sales office in the USA.  The fax denotes that these are qualification samples, automotive spec, and for a particular customer.  That customer is Chrysler (the automotive company now owned by Fiat).

Fax from Hitachi Japan stating use of the HD6801 samples

Also included on the fax is an original Japanese date stamp (June 1982 (Showa year 57)) .  These 6801s were fresh off the production line, having been made only a few weeks earlier.   The fax states these are for Chrysler in Huntsville, AL. with a reminder that they are “Not for Detroit” (where most of Chrysler production was.  That is an interesting addition, and important, as Chrysler did (it closed in 2011) have a very large presence in Huntsville, AL.  Huntsville is known as Rocket City, home of the Redstone Arsenal, where a large amount of US rocket, missile, and space engineering have taken place.  It was also the home of Chrysler Electronics (as well as most all of Chrysler’s military and space programs.  It was Chrysler who built the Saturn 1 and Saturn 1B upper stages for the NASA Apollo program.  Chrysler Electronics also built much of the Grown system electronics for the Apollo program as well as vehicle testing equipment for the M1 tank, the M2/3 Bradley and a host of other military programs.

Chrysler SERV – Space Shuttle Concept

Chrysler also proposed the Single-stage Earth-orbital Reusable Vehicle (SERV) during the design phase of what became the Shuttle program.

In the early 1970’s electronic use in cars was growing rapidly, leading Chrysler to greatly expand their presence in Huntsville.  These 6801s were likely for testing for cars, though it is unclear if Chrysler actually used the 6801 in their vehicles as ECUs from the mid-80’s all seem to be running the 6803 and 6805 MCUs.  Maybe if I find an early 80’s Chrysler I’ll tear out the ECU and find out.

 

November 22nd, 2017 ~ by admin

CPU of the Day: DEC LSI-11 Chipset

LSI-11 Chipset with EIS/FIS Chip – 1976-1977

Back in 2014 we discussed the Western Digital WD/9000 Pascal Microcomputer system.  Today we’ll look at the LSI-11 chip set, the basis of the Pascal.  Back in 1974 DEC (Digital Equipment Corporation) contracted Western Digital to design and build a 16-bit chipset to emulate the Bipolar PDP-11/05 Minicomputer.  Western Digital was paid $6.3 million for the work, and would be allowed to market and sell the resulting chipset themselves, as well as grant license to it to others (including DEC).

The LSI-11 was to be a 16-bit chipset, but was based around a 8-bit Data chips (the 1611).  The 1611 has an 8-bit ALU , 26 8-bit registers and a microinstruction register.  This is controlled by the 1621 control chip, which interprets macroinstructions from handles all the timing, as well as interrupts.  The 1621 control chip is what allows the 8-bit 1611 to be used as a 16-bit processor.  The chips are connected by an 18-bit  microinstruction bus, and a 16-bit address/data bus handles access to the rest of the system (memory/I/O).  Each microm is a 512 Word by 22-bit ROM, which can hold 80 instructions.  It is these MICROMs that allow the WD MCP1600 to function as a PDP-11/05.  The instructions in the the MICROMs (2 are required for the LSI-11) emulate the PDP-11 instructions.

DEC M7264 LSI-11 KD11-L Board from PPD- 11/03

First production of the LSI-11 chipset began in March of 1975 with shipments commencing that year.  The PDP-11/03 based on this chipset was released later that year.  The KD-11 M7264 board formed the hear of the 11/03 (as well as other DEC systems).  In typical DEC fashion it came in many flavors with different amounts of memory, as well as different instruction support.  This was completely due to the design of the LSI-11 chipset and its MICROMs .  The basic LSI-11 need 2 MICROMs to handle the basic PDP-11 instructions, the chipset however supported 4.  This mena that more instructions could be added.  One of the most common and useful additions was the EIS/FIS (Extended Instruction Set/Floating Point Instruction Set) microm.  This added 8 more instructions including MUL, DIV, FADD, FSUB, FMUL, FDIV and 2 register shifts (ASH, ASHC).  Adding the EIS/FIS chip to a standard KD-11-F board turned it into a KD-11-L (like the one pictured).

Western Digital 1611 Die –
Pauli Rautakorpi

There were other MICROMs available as well.  This included a set of 2 for support of DIBOL (Digital Business Oriented Language), a DEC language similar to COBOL.  Since the DIBOL chipset needed 2 chips a system could support DIBOL, OR EIS/FIS but not both.  MICROMs were revised as bugs were found, or faster ways of handing an instruction were made.  MICROMs revisions could also be made to support different PCB revisions.  In some ways they played the part of firmware to the PCB, as well as the instruction set for the processor.  In this way many MICROMs are specific to PCB etch revisions and other revisions of the system outside of the processor itself.  Matching the correct MICROMs, as well as Control and Data chips to the correct board is a bt of a task, and take several dozen pages of the LSI-11 maintenance manual.

Here are a few part #s to help sort things out

Data Chip
DEC 1611
Control Chip
DEC 2007C
MICROMs
MICROM 1 3010D/A
MICROM 2 3007D
EIS/FIS 3015D
Notes
21-11549-01 23-008B5-00 STD INST 1
21-15579-00 (1611H) 23-003C4-00 23-007B5-00 STD INST 2
21-16890-00 (1611H) 23-002C4-00 23-003B5-00 EIS/FIS
23-001C3 CP1621B14 23-009B5-00 EIS/FIS
23-001C2-01 CP1621B451 23-001B5-00 CP1631B103 STD INST 1
23-002B5 CP1631B073 STD INST 2
 23-091A5-01 CP1631B153 EIS/FIS
23-004B5 DIBOL 1
23-005B5 DIBOL 2
23-008A5-01 CP1631B-10 STD INST 1
23-007A5-01 CP1631B-07 STD INST 2

DEC M7270 LSI-11 – 1982 – All WD Chips

There are more to be found as DEC and Western Digital made many versions.  In early 1976 Western Digital licensed the MCP1600 chipset design to National Semiconductor, in exchange for some RAM technology licensing.  It is unclear if National actually made any of the MCP1600 chipset.  By 1977 DEC had started to produce the LSI-11 chip itself while continuing to source parts from Western DIgital as well.  It is common to see LSI-11 boards with DEC and WD chips mixed well into 1982.

The popularity of the PDP-11 in the 1970’s resulted in many customers for the LSI-11 based PDP’s, and their use continued well into the 1990’s with many systems continuing to be used today.  As with many such systems, they found use in industrial control and automation, where they continue to work.

November 14th, 2017 ~ by admin

CPU of the Day: Fairchild F9445: The MicroFlame Flames Out

Fairchild 9445DM – 1983 Military Temp Range

In the 1970’s many companies began to make processors based on mainframe architectures of the time. Data General with the creation of the mN601 MicroNova, TI with the TMS9900, DEC with the LSI-11 and others.  This set the stage for a pretty large showdown, as what happens when a company other then the original mainframe company creates a processor that is compatible?  This is what began to happen in the late 1970’s, and with the release of Fairchild F9440 MICROFLAME.  We’ll quote directly from the F9440 datasheet “Though structurally different from the CPUs of the Data General NOVA line of minicomputers, the 9440 offers comparable performance and executes the same instruction set.”  Specifically the bi-polar F9440 could

DGC mN602E – MicroNova – Data Generals Own single chip Nova

run most the code from the very popular Data General Nova 2 computer system.  Obviously, as Fairchild states, it is structurally different, as its Fairchilds own hardware LSI implementation.  The idea that an instruction set could be copyrighted was already being tested, and by all appearances at the time it was assumed that an Instruction set, could not be copyrighted.  This certainly helped in the wide adoption late on of x86.  A different way of protecting computer architectures had to be created then.

The first salvo was fired by Data General, in a lawsuit claiming that Fairchild’s F9440 enticed DG users to break their software license agreements.  DG’s way of ensuring they had control of their customers was to add a section in the software license agreement that the software could ONLY be ran on Data General hardware, even if it COULD run on a Fairchild F9440 (or any other hardware) it was a violation of the license to do so.  In 1978 Fairchild counter-sued, claiming that such a license was anti-competitive and seeking $10 Million in damages as a result of DG’s original suit.

9445 DIe shot (partial)

To add fuel to the fire, Fairchild announced the F9445, the MICROFLAME II.  The F9445 was built with the same I3L (Isoplanar Integrated Injection Logic) technology but on a 2-Micron process instead of the 3-Micron process of the 9440 and contained over 5000 gates.  The F9445 could was compatible with the Nova 3 and Fairchild claimed it would be 10 times faster then the Nova 3.   The F9445 was announced in 1978 but development issues (this was one of the largest, fastest bi-polar designs) took some time and led to many delays. In 1979 Fairchild, low on cash, was purchased by  Schlumberger Limited, an oil field services company, for $425 million (Exxon responded by buying Zilog in 1980).  Production of the F9445 finally began in the first half of 1981, with deliveries beginning late in the year.  Initial devices ran at 16MHz (an increase from 12MHz in the original 9440) and 20 and 24MHz versions were released later.  The F9445 required a single +5VDC supply and a 300mA current supply dissipating about 1.5W (compared to 1W for the 9440).  The MICROFLAME II was aptly named, they ran rather hot (not unusual for their technology though). Like the F9440 the 9445 is a 16-bit processor and could directly address 128K of memory.  It adds a stack pointer and hardware multiply, while retaining the same 50 instructions from the 9440 but increases the addressing modes supported from 8 to 11 (needed to emulate the Nova 3).

Fairchild F9450-15DC – MIL-STD-1750A processor based on the architecture of the F9445

Interestingly the F9445 provided the base for another Fairchild processor.  The F9445 took Nova instructions, decoded them and ran them on its hardware, it was, in other words, a micro-coded processor.  Microcoded processors can be useful as the microcode can be changed to support an entirely different instruction set. That’s exactly what Fairchild did with the F9450, a processor designed to execute the just released MIL-STD-1750A 16-bit instruction set.

Data General was not pleased, so again sued, claiming that Fairchild probably stole proprietary information in order to design the F9445.  Fairchild was not alone in the action as their were other companies who made Nova emulating hardware, as well as those who made software that would run on a Nova.  The lawsuits (no less then 11 of them) continued well into the 1980’s.  By 1986 Data General was struggling, the case continued, and was not going in their favor.  In September of 1986, a month before the trial for damages was to begin, Data General settled, paying Fairchild $52.5 million.  Eight years after the fireworks began, the original F9440 MICROFLAME had not been made in years, the Nova 2 and Nova 3 were no longer made as well.  The lawsuits destined the F9440 and the F9445 to failure, but they made their mark in setting precedent in lock-in, and how Instruction Sets can be used.

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September 30th, 2017 ~ by admin

Processing the Page Turn

DSC Page Turn Processing Board. 6x 16bit ALUs – 1989

This board isn’t strictly a CPU but it is a processor of sorts.  I actually purchased this board as it was described as a DEC board, with not a great picture, having not seen a DEC board with LOGIC ALUs on it I bought it.  When it arrived I found it wasnt DEC at all but DSC, Digital Services Corporation.  DSC was a video effect company formed in the early 1980’s and later bought out by Chyron, one of the leaders of television video effects hardware.

In the 1980’s, effects on television were generally done in hardware, and required rather specialized hardware for each type of effect.  The most primitive were CG (Character Generators) that added captions typically to the lower third of the screen for a broadcast, like the name of the person speaking, etc.  As hardware capabilities increased, other effects could be generated, such as a video or image overlay, perspective changes or the page turn effect.

Logic L4C381GC-40 – 4x4bit ALU’s implemented in CMOS

These effects generally were handled by an effects processing system, with each effect having its own board in the system responsible for that effect.  Adding an effect required buying an effects board and installing it in the system.  This particular board from DSC handles the Page Turn Effect.  This is where one video transitions to another video with the look of a turning page.  It requires 3 inputs, the first video, the second video being turned to, and a typically solid color/image that represents the back of the page.  Here is a quick example on YouTube.  Today this can be handled by most any video editing software on a general purpose computer, but in 1989 there wasn’t a computer that could do this in near real time.

This board is built around 6 LOGIC L4C381GC-40/55 ALUs and 6x LOGIC LMU216JC-55 Multipliers.  The 4C381s are a 16-bit CMOS ALU, based on 4 74381 4-bit ALU,s a Carry Generator and interface logic.  Basically 1970’s technology updated to CMOS.  They handle 16 bit Addition, Subtraction and basic logic (XOR/OR/AND).  The LMU216s are 16 x 16-bit Parallel Multipliers.  They are the equivalent of the old AMD Am29516 that was cloned by TRW, Cypress and IDT.

LOGIC LMU216JC-55 – 16×16 CMOS Multiplier

The rest of the board consists of 6x64Kb or Video RAM, shift registers, and all the control logic (in PALs) to provide the instructions for the ALUs and multipliers.  The arrangement of the board suggests a 64-bit computation section and a 32-bit section.  Just as in the 1970’s the ALUs and multipliers have been used to make a custom processor, with a very specific instruction set and purpose and do so at a speed that would be compatible with broadcast television.  Sitting on one’s couch in the 1980’s watching TV and seeing a cool page turn effect one would think, ‘Hey that’s cool!’, yet have no idea that an entire processing system had to be designed, built and coded for that one second of television.

Russian Translation now available here by Vlad Brown

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