Archive for the 'CPU of the Day' Category

December 13th, 2014 ~ by admin

TriMedia TM-1300: VLIW Processor for the World

TiMedia TM-1300 - Marketing Sample

TiMedia TM-1300 – Marketing Sample

The roots of TriMedia start in 1987 at Philips with Gerrit Slavenburg (who wrote actual forwards for most of the Datasheets) and Junien Labrousse as the LIFE-1 processor.  At its heart it was a 32-bit VLIW (Very Long Instruction Word) processor. VLIW was a rather new concept in the 1980’s, and really didn’t catch on until the late 90’s.  Intel’s i860 could run in superscalar, or VLIW mode in 1989 but ended up a bit of a flop.  TI made the C6000 lince of the TMS320 DSP which was VLIW based.  By far thos most famous, or perhaps infamous, VLIW implementation were the Transmeta, and the Itanium, both of which proved to be less then successful in the long run (though both ended up finding niche markets).

TriMedia, released their first commercial VLIW product in 1997, the TM1000.  As the name suggests, TriMedia Processors are media focused.  They are based around a general purpose VLIW CPU core, but add audio, video and graphics processing.  THe core is decidedly not designed as a standalone processor.  It implements most CPU functions but not all, for example, it supports only 32-bit floating point math (rather than full 64 or 80 bit).

The TM-1300 was released in 1999 and featured a clock speed of 166MHz @ 2.0V on a 0.25u process.  At 166MHz the TM-1300 consumed about 3.5W, which at the time was relatively low.  It had 32K of Instruction Cache and 16K of Data Cache. As is typical of RISC processors the 1300 had 128 general purpose 32-bit registers. The VLIW instruction length allows five simultaneous operations to be issued every clock cycle. These operations can target any five of the 27 functional units in the processor, including integer and floating-point arithmetic units and SIMD units.

The above picture TM-1300 was a marketing sample handed out to the media during the Consumer Electronics Show for the processors release in 1999.  It is marked with the base specs of the chip as well as CES SAMPLE.  Likely these were pre-production units that didn’t meet spec or failed inspection, remarked for media give-aways.

Read More »

December 8th, 2014 ~ by admin

Makings of a Comet: The VAX 11/750

DEC 608B 19-14682-00 VAX750 ALP - 4- bit slice

DEC 608B 19-14682-00 VAX750 ALP – 4- bit slice

In the mid-1970’s DEC saw the need for a 32-bit successor to the very popular PDP-11.  They developed the VAX (Virtual Address eXtension) as its replacement.  Its important to realize that VAX was an architecture first, and not designed from the beginning with a particular technological implementation in mind.   This varies considerably from the x86 architecture which initially was designed for the 8086 processor, with its specific technology (NMOS, 40 DIP, etc) in mind.  VAX was and is implemented (or emulated as DEC often called it) in many ways, on many technologies.  The architecture was largely designed to be programmer centric, writing software for VAX was mean to be rather independent of what it ran on (very much like what x86 has become today).

The first implementation was the VAX 11/780 Star, released in 1977, which was implemented in TTL, and clocked at 5MHz.  TTL allowed for higher performance, but at the expense of greater board real estate as well as somewhat less reliability (more IC’s means more failure points). It also cost more, to purchase, to run, and to cool.

DEC followed the Star with the 11/750 Comet in 1980.  This was a value version of the Star.  It ran at only 3.12MHz (320ns cycle time) but introduced some new technology.  Part of the ‘value’ was a much smaller footprint.  The TTL had been replaced by bi-polar gate arrays.  Over 90% of the VAX architecture was implemented in the gate arrays, and there was a lot of them, 95 in a complete system with the floating point accelerator (28 arrays).  The CPU and Memory controller used 55 while the Massbus (I/O) used an additional 12 gate arrays.  The 95 gate arrays though replaced hundreds of discrete TTL chips.  And as a further simplification they were all the same gate array.

Read More »

Tags:
,

Posted in:
CPU of the Day

November 21st, 2014 ~ by admin

When a Minicomputer becomes a Micro: the DGC microNOVA mN601 and 602

DGC logoThe late 1960’s and early 1970’s saw the rise of the mini-computer.  These computers were mini because they no longer took up an entire room.  While not something you would stick on your desk at home, they did fit under the desk of many offices.  Typically there were built with multiple large circuit boards and their processor was implemented with many MSI (medium scale integration) IC’s and/or straight TTL.  TTL versions of the 1970’s often were designed around the 74181 4-bit ALU, from which 12, 16 or even 32-bit processor architectures could be built from.  DEC, Wang, Data General, Honeywell, HP and many others made such systems.

By the mid-1970’s the semiconductor industry had advanced enough that many of these designs could now be implemented on a few chips, instead of a few boards, so the new race to make IC versions of previous mini-computers began.  DEC implemented their PDP-11 architecture into a set of ICs known as the LSI-11. Other companies (such as GI) also made PDP-11 type IC’s.  HP made custom ICs (such as the nano-processor) for their new computers, Wang did similar as well.

Data General was not to be left out.  Data General was formed in 1968 by ex DEC employees whom tried to convince DEC of the merits of a 16-bit minicomputer.  DEC at the time made the 12-bit PDP-8, but  Edson de Castro, Henry Burkhardt III, and Richard Sogge thought 16-bits was better, and attainable.  They were joined by Herbert Richman of Fairchild Semiconductor (which will become important later on.)  The first minicomputer they made was the NOVA, which was, of course, a 16-bit design and used many MSI’s from Fairchild.  As semiconductor technology improved so did the NOVA line, getting faster, simpler and cheaper, eventually moving to mainly TTL.

Read More »

November 15th, 2014 ~ by admin

Apple A8X Processor: What does an X get you?

Anandtech has an excellent article on the new Apple A8X processor that powers the iPad Air 2.  This is an interesting processor for Apple, but perhaps more interesting is its use, and the reasoning for it.  Like the A5X and A6X before it (there was no A7X) it is an upgrade/enhancement from the A8 it is based on.  In the A5X the CPU was moved from a single core to a dual core and the GPU was increased from a dual core PowerVR SGX543MP2 to a quad-core PowerVR SGX543MP4.  The A6X kept the same dual core CPU design as the A6 but went from a tri-core SGX543MP3 to a quad core SGX554MP4.  Clock speeds were increased in the A5X and A6X over the A5 and A6 respectively.

The A8X continues on this track.  The A8X adds a third CPU core, and doubles the GX6450 GPU cores to 8.  This is interesting as Imagination Technologies (whom the GPUs are licensed from) doesn’t officially support or provide an octa-core GPU.  Apple;s license with Imagination clearly allows customization though.  This is similar to the ARM Architecture license that they have.  They are not restricted to off the shelf ARM, or Imagination cores, they have free reign to design/customize the CPU and GPU cores.  This type of licensing is more expensive, but it allows much greater flexibility.

This brings us to the why.  The A8X is the processor the the newly released iPad Air 2, the previous iPad air ran an A7, which wasn’t a particularly bad processor.  The iPad Air 2 has basically the same spec’s as the previous model, importantly the screen resolution is the same and no significantly processor intense features were added.

When Apple moved from the iPad 2 to the iPad (third gen) they doubled the pixel density, so it made sense for the A5X to have additional CPU and GPU cores to handle the significantly increased amount of processing for that screen. Moving from the A7 to the A8 in the iPad Air 2 would make clear sense from a battery life point of view as well, the new Air has a much smaller batter so battery life must be enhanced, which is something Apple worked very hard on with the A8.  Moving to the A8X, as well as doubling the RAM though doesn’t tell us that Apple was only concerned about battery life (though surely the A8X can turn on/off cores as needed).  Apple clearly felt that the iPad needed a significant performance boost as well, and by all reports the Air 2 is stunningly fast.

It does beg the question though? What else may Apple have in store for such a powerful SoC?

October 30th, 2014 ~ by admin

SGS-Ates M380 and GI LP8000 – 8 Bits for Europe

SGS-Ates M380B1 - 1977

SGS-Ates M380B1 – 1977

In the 1970’s the computer age was booming.  New processor designs were being pushed out by the month, and computers to use them were being designed and outdated just as fast.  Not all markets were growing as fast as the American market, or could support the newest, most complex, and expensive designs.  Thus, it was common for semiconductor companies to design chips specifically for these markets.  Europe was considered one of these markets, where simpler more affordable devices were easier to sell, thus CPUs were made specifically for the European market.  Many of these designs are still nearly impossible to find outside of Europe.

General Instruments was one such company.  Their premier processor, the CP1600, was a 16-bit deign based on the PDP-11.  It was one of the first NMOS 16-bit processors (along with the TI9900) and was released in 1975.  GI also had the PIC line of 8-bit MCUs for control oriented tasks, which is still in production today.  GI wanted a design for the European market so in 1976 released the LP8000, LP for Logic Processor.  The LP8000 was a 3-chip simple processor and cost a mere $10.  It could execute 48 instructions (including ADD, but subtraction was not supported directly) at a clock speed of 800 kHz and was made on a PMOS process. The chipset consisted of the LP8000 processor which contained the ALU and 48 8-bit registers as well as the accumulator a 6-bit address bus and 8-bit of I/O.  Combining the 6-bit address and 8-bit I/O busses allowed the LP8000 to directly address 16K of memory.  The 11-bit Program Counter was contained off chip, on the LP6000 which also contained an additional 16 lines of I/O and 1K of ROM for program storage.  Clock generation was provided by the LP1030 and memory expansion was handled by the LP1000 (which also includes a 11-bit PC for interfacing up to 2K of memory) while the LP1010 handled I/O expansion.  In order to be successful in Europe GI needed to find a European partner who could make, market and sell the design.

GI LP8000

GI LP8000

That partner ended up being SGS-Ates of Italy (which later would become ST Microelectronics).  SGS-Ates second sourced the LP8000 as the M38 (or M380) series.  The M380 was the processor element, while the M382 was the 1K ROM equivalent of the LP6000.  In addition SGS-Ates made the M381 which had 18 bytes of RAM and 768 bytes of ROM as well as the PC.  Like the LP8000 the M380 drew about 1 Watt of power and required a +5V and -12V supply (or a -5V and -17V).  The M380 was rather short lived as SGS-Ates soon licensed the Zilog Z80 which was a much more powerful, yet still inexpensive, design.  When SGS-Ates purchased Mostek from United Technologies they added yet another 8-bit design, the F8, which Mostek had licensed from Fairchild.  These processors quickly replaced the M380/LP8000 and with no market, it faded into obscurity.

September 27th, 2014 ~ by admin

National Semiconductor: The COP before the COPS

National Semiconductor MM5782N - 400KHz 1976

National Semiconductor MM5782N – 400KHz 1976

In August we detailed the COP2404 and the COP400 line of 4-bit microcomputers by National Semiconductor.  This NMOS design originated in 1977 and was made for over 30 years.  It, however, was not the the first COP line of National Semiconductor.  In fact the COP400 family was referred to as the COPS II for a brief period in the 1970’s.  If the COP400 was the second in line then what was the ORIGINAL COP microcomputer?

That would be the COPS I of course, better known as the MM5781/2 and its derivatives, the MM5799, MM57140 and MM57152.  These microcomputers were released in 1976 and were made on a volume PMOS process.  They were designed to be inexpensive and simple to use.  The design of the 5781/2 actually started with the MM5734 which was a single chip accumulating calculator chip.  The differences are not as big as one may think.  A multi-function calculator with memory needs an ALU, registers, ann accumulator and instruction decoding, as well as very limited memory and fairly extensive I/O (to run the display and read inputs from the keyboard).  National saw this as an opportunity to capture a bit of the low-end market.  They already had the IMP-16 for their high end, the SC/MP for the mid range, as well as second sourced Intel MCS-4 and MCS-80.  What they lacked was something to compete with the likes of the WD1872 and the TI TMS1000 series as well as the rise of the Japanese 4-bit solutions from NEC, Toshiba and Sanyo.

The 5781/2 was a 2 chip solution, together they formed a microcomputer.  The 5781 contained the program ROM (2048 x 8 bits), as well as the program counter and some control logic.  The 5782 was contained the full ALU, the accumulator, the instruction decoder, and 160×4 bits of RAM.  It could execute 33 different instructions.  Clock speed was 70-400KHz and was provided by an off-chip oscillator.

National Semiconductor MM5799 - Single chip COPs

National Semiconductor MM5799 – Single chip COPs

National combined the 5781/2 into a single 28 pin chip called the MM5799.  It contained all the logic of the 5781/2 but with a smaller amount of RAM (96 x 4 bits) and ROM (1500 x 8 bits). Clock speed remained the same but the instruction set was expanded slightly to 41 instructions.  Two other versions were also made that had more extensive I/O.  The MM57140 which had build in LED drivers, and the MM57152 which was the same, but had built in fluorescent display drivers (this was the 1970’s after all). The ‘140 and ‘152 had 36 instructions 55 x 4 bits of RAM and 630 x 8 bits of ROM. Maximum clock speed was also reduced to 280KHz.

Read More »

August 30th, 2014 ~ by admin

Improve Technologies Make-it 486 – 286 Upgrade

Cx486SLC/e-33MP Based Improve Technologies Make-It 386 for a 286

Cx486SLC/e-33MP Based Improve Technologies Make-It 386 for a 286

Improve Technologies (IT) was a company that existed from 1991-1997.  They were one of the many (to include Cyrix, Evergreen, PNY, Gainbery, etc) that made processors for upgrading 286, 386 and 486 computers.  Processor upgrades are no longer commonplace, becoming nearly non-existent (except for such things as 771 to 775 adapters).  Today computer hardware has become so inexpensive that upgrading more often just consists of purchasing a whole new computer, or at least new motherboard, RAM, and CPU, all at a price of a few hundred dollars.

In the early to mid-90;s however, a computer system cost 2-$3000, so replacing it every few years was not financially viable for many people.  Thus processor upgrades, they were designed to replace a CPU with the next generation CPU (with some limitations) at a price of a few hundred dollars.

In 1976 TranEra was founded in Utah. TransEra is an engineering solutions company, they are built on seeing a technological problem, and engineering a solution, whatever that may be.  They began by making add-on for Tektronix test gear and HP-IB interface equipment.  In 1988 they released HTBasic, a BASIC programming language (based on HP’s Rocky Mountain BASIC) for PC’s.  This is what TransEra became perhaps best known for, as they continue to develop and sell HTBasic.  It was TransEra who developed the Improve Technologies line of upgrades.  They saw a problem, and engineered a solution.

Read More »

Tags:
,

Posted in:
CPU of the Day

August 25th, 2014 ~ by admin

National Semiconductor COP2404 – Dual Core Processor from 1982

National Semiconductor COP2404N - Dual core processor

National Semiconductor COP2404N – Dual core processor

National Semiconductor introduced the COPS series of 4-bit processors in 1977.  COPS came from National’s calculator line of chips, and for a short time were known as Calculator Oriented Processors, however this was rapidly changed to Control Oriented Processor System (COPS).  These 4-bit microcontrollers, as their name suggests, were for controlling various consumer devices.  They were used in all sorts of devices from game consoles, to dishwashers.  In the early 1980s National began producing them in CMOS versions, and in 1988 they extended the line to 8-bit (the COP8 family).

COP2404 Block Diagram - 2 Cores with shared memory. - Click to enlarge

COP2404 Block Diagram – 2 Cores with shared memory. – Click to enlarge

In 1981 the COP2404 (and 2440) were announced, with availability beginning in 1982.  The COP2404 was on the top end of the COPS line, it was found that some real time control operations were better served by 2 microcontrollers, so why not design 2 into one.  The 2404 is a dual core processor, with two complete COPS404 cores on one die, sharing I/O and RAM. (The 2440 also included ROM).  True to multi-core form, the memory was shared, meaning the processors could work independently or pass data to each other, including task handoffs if the programmer so desired.  This wasn’t implemented in hardware, but it wasn’t forbidden either, meaning a programmer could do some pretty complicated task management with the dual CPU cores.

The 2404 was packed in a 48 pin PDIP, and was designed as a development device for use with external program memory (EPROM typically).  Production devices were the 2440 (40 pin) 2441 (28 pin) and 2442 (24 pin) which all had 2K of ROM on die.  All included 160×4 bits of RAM and had an instruction cycle of 4usec (using a 4MHz clock, as each instruction took 16 cycles).  They were manufactured on a 3-micron NMOS process (originally, likely shrunk over time).

As technology progressed it became easier to handle multiple real time tasks with a single, faster controller, with good hardware interrupt handling, but for a time, their was a dual-core processor.  The COPS series continued to be sold by National until 2011, when they were bought by Texas Instruments.  While no longer actively marketed, several members of the COP8 line are still being sold.

August 15th, 2014 ~ by admin

Four-Phase Systems AL1 Processor – 8-bits by Lee Boysel

Four-Phase Systems AL-4 - 1000+ gates 8-bits

Four-Phase Systems AL-4 – 1000+ gates 8-bits

In today’s tech economy there are companies that serve as incubators for startups, such institutions as Y-Combinator and Techstars entire purpose is to help develop emergent tech companies.  In the 1960’s there was also tech incubators, perhaps the best known is Fairchild.  The difference is that Fairchild was not designed to be an incubator, nor were they trying to be.  The bureaucracy of such a large corporation allowed many engineers in somewhat marginal positions to work extensiely on projects of their own. Projects that perhaps were not directly beneficial to Fairchild, but close enough related to slip under managements noses.  Many of the ‘great’ semiconductor companies were started by former Fairchild employees, Robert Noyce, co-founder of Intel, being perhaps the most famous.

Lee Boysel started work at Fairchild in 1966 after working at several other companies semiconductor departments.  Boysel had one main focus, MOS.  MOS (Metal-Oxide-Semiconductors) were very new in the 1960’s and their potential was not well understood.  Most IC’s were designed using Bipolar technology but Boysel saw the potential of MOS and worked at Fairchild to perfect its processes.  He designed a 256-bit RAM in MOS< as well as an 8-bit full adder, as well as the first MOS IC with over 100 gates.  None of these designs were of great commercial success, but that was Fairchild’s problem, not Boysel’s. Boysel was building the foundations for his greater plans, plans that would be realized only after leaving Fairchild.

Boysel left Fairchild in 1968, to build a new company known as Four-Phase Systems.  Four-Phase was named after the 4-phase clocking system used in the MOS logic Boysel had designed.  Boysel’s goal was to build a single chip computer using MOS and use it to power systems to rival the likes of Data General and IBM.  Initial funding of $2 million was provided, somewhat ironically, by Corning Glass works, who also owned a large portion of Signetics.  Initial production of Boysel’s designs was by yet another Fairchild incubated startup known as Cartesian inc.  Cartesian was offered foundry services that duplicated Fairchild;s MOS process.  This saved Four-Phase from having to build there designs for a completely new process.

Read More »

August 10th, 2014 ~ by admin

An Interesting Fujitsu MCM Pentium Module

Fujitsu MRN-3545 (100) 100MHz Pentium with no L2 Cache

Fujitsu MRN-3545 (100)
100MHz Pentium with no L2 Cache

We have seen Fujitsu MCM Pentiums before.  120MHz, 133MHz 150MHz and MMX ones.  One is pictured in the article on the MicroModule Systems Gemini here.  The 100MHz module is similar, though it is missing the L2 cache tag RAM (256 kbit chip on the top of the package) as well as the 2 cache RAM chips normally installed on the backside of the module.  It would appear that Fujitsu offered these modules with the cache being optional.  There was a 133MHz version (MRN-3548) with cache, and one (MRN-3549) without cache.

These processors were typically used in environmentally challenging environments.  Panasonic famously used them in their ToughBook CF25, the beginning of a line of highly durable laptop in 1996.  Some of these applications were sealed environments, they did not have vents, or active cooling.  This obviously  makes cooling a challenge.  Removing the L2 cache, while causing a significant hit in performance, would alleviate some of the heat generation.

We consider L2 cache to be essential, but many applications do not require it.  Intel infamously removed the L2 Cache completely from the first Celeron processors and while they worked, they were not particularly competitive performance wise.  When competing against wind, rain dirt, and droppage? L2 cache may not be so important