can you take phenergan suppository while pregnant phenergan half life po adderall and provigil interactions taking provigil with food provigil online europe

Archive for the 'CPU of the Day' Category

January 2nd, 2020 ~ by admin

Chips in Space: Making MILSTAR

Milstar Satellite

Back in the late 1970’s having a survivable space based strategic communications network became a priority for the US Military.  Several ideas were proposed, with many lofty goals for capabilities that at the time were not technologically feasible.  By 1983 the program had been narrowed to a highly survivable network of 10 satellites that could provide LDR (Low Data Rate) strategic communications in a wartime environment.  The program became known as MILSTAR (Military, Strategic, Tactical and Relay) and in 1983 President Reagan declared it a National Priority, meaning it would enjoy a fair amount of freedom in funding, lots and lots of funding.  RCA Astro Electronics was the prime contractor for the Milstar program, but during the development process was sold to GE Aerospace, then Martin Marietta, which became Lockheed Martin before the 3rd satellite was launched.  The first satellite was suppose to be ready for launch in 1987, but changing requirements delayed that by 7 years.

Milstar Program 5400 series TTL dies

The first satellite was delivered in 1993 and launched in February of 1994.  A second was launched in 1995 and these became Milstar-1. A third launch failed, which would have carried a hybrid satellite that added a Medium Data Rate (MDR system).  Three Block II satellites were launched in 2001-2003 which included the MDR system, bringing the constellation up to 5.  This provided 24/7 coverage between the 65 degree N/S latitudes, leaving the poles uncovered.

TI 54ALS161A

The LDR payload was subcontracted to TRW (which became Northrup Grumman) and consisted of 192 channels capable of data rates of a blazing 75 – 2400 baud.  These were designed for sending tasking orders to various strategic Air Force assets, nothing high bandwidth, even so many such orders could take several minutes to send.  Each satellite also had two 60GHz cross links, used to communicate with the other Milstar sats in the constellation.  The LDR (and later MDR) payloads were frequency hopping spread spectrum radio system with jam resistant technology.  The later MDR system was able to detect and effectively null jamming attempts.

The LDR system was built out of 630 LSI circuits, most of which were contained in hybrid multi layer MCM packages.  These LSIs were a mix of custom designs by TRW and off the shelf TTL parts.  Most of the TTL parts were sourced from TI and were ALS family devices (Advanced Low Power Schottky), the fastest/lowest power available.  TI began supplying such TTL (as bare dies for integration into MCMs) in the mid-1980’s.  These dies had to be of the highest quality, and traceable to the exact slice of the

Traceability Markings

exact wafer they came from. They were supplied in trays, marked with the date, diffusion run (a serial number for the process and wafer that made them) and the slice of that wafer, then stamped with the name/ID of the TI quality control person who verified them.

These TTL circuits are relatively simple the ones pictures are:
54ALS574A Octal D Edge Triggered Flip flop (used as a buffer usually)
54ALS193 Synchronous 4-Bit Up/Down Binary Counters With Dual Clock
54ALS161A Asynchronous 4-Bit Binary Counters

ALS160-161

Looking at the dies of these small TTL circuits is quite interesting.  The 54ALS161A marking on the die appears to be on top of the a ‘160A marking.  TI didn’t make a mistake here, its just that the the 160 and 161 are essentially the same device.  The 161 is a binary counter, while the 160 was configured as a decade counter.  This only required one mask layer change to make it either one.

ALS573 and ALS574 die

Similarly with the 54ALS574, which shares a die with the more basic ‘573 D type transparent Latch.  This was pretty common with TTL (if you look at a list of the different 7400 series TTL you will notice many are very similar with but a minor change between two chips).  It is of course the same with CPUs, with one die being able to be used for multiple core counts, PCI0E lanes, cache sizes etc.

Together with others they perform all the function of a high reliability communications systems, so failure was not an option.  TI supplied thousands upon thousands of dies for characterization and testing.  The satellites were designed for a 10 year lifetime (it was hoped by them

Milstar Hybrid MCM Command Decoder (picture courtesy of The Smithsonian)

something better would be ready, no doubt creating another nice contract, but alas, as many things are, a follow on didn’t come along until just recently (the AEHF satellites).  This left the Milstar constellation to perform a critical role well past its design life, which it did and continues to do.  Even the original Milstar 1 satellite, launched in 1994 with 54ALS series TTL from the 1980s is still working, 25 years later, a testament to TRW and RCA Astro’s design.  Perhaps the only thing that will limit them will be the available fuel for their on-orbit Attitude Control Systems.

While not necessarily a CPU in itself these little dies worked together to get the job down.  I never could find any of the actual design, but it wouldn’t surprise me if the satellites ran AMD 2901 based systems, common at the time or a custom design based on ‘181 series 4-bit ALUs.  finding bare dies is always interesting, to be able to see into whats inside a computer chip, but to find ones that were made for a very specific purpose is even more interesting.  The Milstar Program cost around $22 Billion over its life time, so one must wonder how much each of these dies cost TRW, or the US Taxpayer?

Tags:
, ,

Posted in:
CPU of the Day

November 1st, 2019 ~ by admin

CPU of the Day: Motorola MC68040VL

Motorola MC68040VL

A month or so ago a friend was opening up a bunch of unmarked packages, and taking die photos and came across an interesting Motorola.  The die looked familiar, but at the same time different.  The die was marked 68040VL, and appeared to be smaller version of the 68040V.  The Motorola 68040V is a 3.3V static design of the Motorola MC68LC040 (It has dual MMUs but lacks the FPU of the 68040).  The 68040V was made on a 0.5u process and introduced in 1995.  Looking closely at the mask revealed the answer, in the form of 4 characters. F94E

Motorola Mask F94E – COLDFIRE 5102

Motorola uses mask codes for nearly all of their products, in many ways these are similar to Intel’s sspecs, but they are more closely related to actual silicon mask changes in the device.  Multiple devices may use the same mask/mask code just with different features enabled/disabled.  The Mask code F94E is that of the first generation Motorola COLDFIRE CPU, the MCF5102.  The COLDFIRE was the replacement for the Motorola 68k line, it was designed to be a 32-bit VL-RISC processor, thus the name 68040VL for VL-RISC. .  VL-RISC architectures support fixed length instruction (like a typical RISC) but also support variable length instructions like a traditional CISC processor.  This allows a lot more code flexibility and higher code density.  While this may be heresy to RISC purists it has become rather common.  The ST Transputer based ST20 core is a VL-RISC design, as is the more modern RISC-V architecture.  The COLDFIRE 5102 also had another trick, or treat up its sleeve.  It could execute 68040 code.

Read More »

October 7th, 2019 ~ by admin

The Forgotten Ones: RISCy Business of Winbond

Winbond W77E58P-40 – Your typical Winbond MCS-51 MCU

Winbond Electronics was founded in Taiwan back in 1987, and is most widely known for their memory products and system I/O controllers (found on many motherboards of the 1990s).  They also made a wide variety of microcontrollers, mostly based on the Intel MCS-51 core, like many many other companies have and continue to do.  They also made a few 8042 based controllers, typically used as keyboard controllers, and often integrated into their Super I/O chips.  So why do I find myself writing about Winbond, whose product portfolio seems admittedly boring?

It turns out, that once upon a time, Winbond decided to take a journey on a rather ambition path.  Back in the early 1990’s they began work on a 32-bit RISC processor, and not an ARM or MIPS processor that were just starting to become known at the time, but a processor based on the HP PA-RISC architecture. This may seem a odd, but HP, in a shift form their previous architectures, wanted the PA-RISC design to be available to others.  The Precision RISC Organization was formed to market and develop designs using the architecture outside of HP.  HP wanted to move all of their non-x86 systems to a single RISC architecture, and to help it become popular, and well supported, it was to be licensed to others.  This is one of the same reasons that made x86 so dominate in the PC universe.  More platforms running PA-RISC, even of they were not HP, meant more developers writing PA-RISC code, and that mean more software, more support, and a wider user base.  Along with Winbond, Hitachi and OKI also developed PA-RISC controllers.  Winbond’s path was innovative and much different then others, they saw the need for easy development as crucial to their products success, so when they designed their first PA-RISC processor, the W89K, they made it a bit special.

Read More »

August 28th, 2019 ~ by admin

Sushi Tacos and Lasers: Marking Intel Processors

Intel ink stamp used for marking chips in the 1970’s

In 1987 Intel became the first semiconductor manufacturer to use lasers to mark all component parts, including ceramic packages (they still used ink for some but had the capability and eventually rolled out laser marking to most all of their assembly/test locations).  Conventional ink marking for ceramic packages required a post-mark ink cure time and production yields ranged from 96%-98% before rework.  That percentage may be good on a school exam, but in the production environment, having to rework 2-4% of everything off the line is unacceptable.  It costs resources, money and time that do not go to making profit.

Intel A80387-20B SX024 remarked with a laser

With lasers, however, the cure operation was not needed and yields increased to better then 99.95%.  Lasers were so consistent that marking became a zero rework process and overall productivity increased by 25%.  Throughput also increased significantly (less rework and lasers are faster) and inspection requirements dropped by 95%.  These lasers were originally developed for ceramic packages but found to work well on plastic packages as well.  They also made remarking significantly easier, old markings could be crossed out with the laser and new marking made.  No stencils, pads or masks were needed, the lasers were programmable and very fast.

Intel continues to use laser marking today (as do most manufacturers).  Intel uses laser marking systems from Rofin-Sinar (now owned by Coherent).  These lasers are typically from the PowerLine E line, which are a diode end-pumped Nd: YVO4 (Neodymium doped yttrium vanadate) diode laser.  These are basically a high ends high power version of the diode lasers used in laser pointers.  Intel went with diode lasers as they were faster, and cleaner then CO2

Intel Package marked SUSHI TACO SALAD. Perhaps the technician was getting hungry while trying to dial in the laser settings.

lasers (at the same power levels).  These lasers typically run in the 10-40Watt range.  Most commonly they are a 532nm laser (green light).  In order to achieve the speeds needed, these marking systems are ran in a pulsed mode, 1-200KHz depending on the speed and material being marked.  This allows the laser to run at very high power, for very short pulses.

This of course requires some tuning, essentially simple trial and error to find the right setting for a given material.  Today’s packages are very thin, and marking on the organic substrate (or the silicon die itself) must be done in a way that leaves the markings visible, but does not damage the underlying structure. These markings are often only a few microns deep on silicon and 25 microns on a package, as deeper then th

Motorola PP603 Engineering Sample with ROFIN BAASEL test marking on the die

at is the chips circuitry.

Rofin offers testing and calibration for some of their bigger customers (such as Intel) where they help develop the settings needed.  This results in a lot of ‘oddly’ marked chips.  Companies will ship packages, dies and whatever else needs to be marked to Rofin along with

specifications of the markings (how wide, tall, deep etc) and the systems/settings are worked out to make it workable on the production line.  Anyone that has used a CO2 desktop laser knows they are not the fastest thing around.  An engraving project completion time is measured in minutes.  When marking chips, speed and accuracy are of paramount importance.  Rofin advertises their lasers as such “Our semiconductor marking solutions achieve marking speeds up to 1600 characters/second. Even at a character height of 0.2 mm and line widths of less than 30 µm they still ensure best readability.”

Package with laser settings engraved

Here we have a test chip package from Intel, marked up by Rofin, there is tests of the 3d-Bar code, Lots numbers s-specs and others.  There is also some calibration markings, its useful to engrave the settings used as for the test, as the test.  In this case we see 25k, 650mms and 23.8A.  These are 3 of the fundamental settings for the laser system.  25k is the pulse rate (25KHz) of the laser, 650mms is the speed, or feed rate, 650mm per sec (about 2ft/sec),  thats a relatively slow speed, but probably was one step in the calibration process.  The 23.8A is the current for the laser, in amps.  Its a rather high current compared to say a continuous wave CO2 laser which runs currents in the milliamps, but these are pulsed lasers, so that current is only needed for a fraction of a second.

Marking can also be done on the die itself.  Here we see a sample

Flip chip marking marketing sample by ROFIN SINAR in Tempe, AZ

(probably an actually marketing sample given away to customers) of a flip chip die, with ROFIN SINAR markings on it, and erven their phone number for their location in Tempe, AZ (only a few miles from several fabs in Chandler, AZ (including Intel and Motorola (now NXP)).

As chips become smaller, marking technology continues to evolve with it.  Markings today have become much less about what the consumer sees, and much more about traceability and trackability.  Being able to follow a device through the supply chain, or trace a defective device back to when/where it was produced.  Marking enhancements also play a great role in combating counterfeiting, helping them out of the supply chain.

There is a lot that goes into designing, making, assembling and even marking a computer chip, and often times things that seem the simplest, such as placing marking on a chip, are anything but simple, and just as important as the fabrication of the die itself.

June 1st, 2019 ~ by admin

All Boxed up: Retail Boxed CPU’s

NIB MOS 6502 CPU

New In Box MOS MCS6502 CPU from 1975 (Michael Steil – pagetable.com)

Today most all processors are permanently installed in their device (soldered in) or were taken from a bulk tray and installed by the OEM such as Dell or HP.  AMD has, at least with their higher end CPU’s gotten quite creative with the marking on the chip itself, and both AMD and Intel still offer some pretty amazing retail packaging for their enthusiast processors (the i9 in a dodecahedron package is pretty cool).  There was a time when almost all processors were available in retail packaging.  This was the time of physical computer shops, largely bypassed now by the Internet, where the packaging of a processor helped sell it.

I collect such New In Box (NIB) processors as they are pretty need to see the branding/marketing that went with the CPU’s of years past, and was reminded of this when I saw perhaps one of the oldest NIB CPU’s I have ever seen on Michael Steil’s pagetable.com blog.  An original MOS 6502 processor from 1975 in its original shipping box, as close to NIB as one can get.  MOS’s packaging would make Apple proud with its simplicity and design keeping everything tidy and the MCS6502 visible as soon as the box is opened (I am happy they didn’t use miserable black foam either, so the CPU is pristine after 45 years).  Even the original invoice is included.  $25 for the CPU ($118 in 2019 dollars) and $10 (nearly half the cost of the CPU ($47 in 2019)) for documentation)

Cyrix 83D87 386 FPU

Cyrix 83D87 386 FPU Bundled with Borland Quattro PRO Spreadsheet software (a big thing back in 1992)

Intel started offering retail boxed CPUs with the 8087 coprocessor.  This was really the first chip designed as a user upgrade to their PC (a new thing back then).  Before this Intel’s closest thing to a NOB was University Kits or Dev Kits for various chips/processors.  With the introduction of the PC, and the many thousands of beige box clones that followed, people themselves began buying processors and building computers for themselves at a much greater pace then before.  There was many companies making compatible processors at the time so packaging helped set them apart.  This began with upgrade products, math coprocessors for the 808x, 286 and 386 were the most common (by Intel, AMD, IIT, ULSI. Cyrix and more), but eventually processors themselves started getting the NIB treatment, Intel made OverDrive processors (still technically an upgrade product) for the 486. followed by actual Pentium CPUs in the retail box. By the late 1990’s everything from Celerons to Xeon server processors could be had in Retail box.  Buying a retail boxed Xeon for your rackmount server seems like an odd thing to do, but apparently Intel figured it would need to be done.

Quad AMD Opteron 6128s in Retail Box

Quad AMD Opteron 6128s in Retail Box

Other companies such as AMD, Cyrix and VIA made NIB processors but they are much less common, and in a lot of ways more interesting.  AMD made retail Durons, Athlons, and Opterons, and in one of the most unusual things I have seen for a NIB, an actual 4-pack of Opteron 6128s (pictured). The Opteron 6128 is a 8 core Magny-Cours server processor introduced in 2009 and cost $266 each at that time.  This NIB set is dated late 2011, so would probably be a bit cheaper, but still $800 or so, and the large SWATX motherboards needed to run 4 socket G34 processors require somewhat special cases and PSU’s, but at least you can have  a half terabyte of RAM.  Inside the retail box is 4 smaller boxes, each containing an Opteron 6128 CPU, installation instructions, warranty info, and a case badge (you get 4 total case badges).  It seems this packaging was designed to support different configurations (probable a single Opteron 6128, and duals).

Tags:
, ,

Posted in:
CPU of the Day

April 18th, 2019 ~ by admin

Tiered up for 3D-FPGAs: The Story of the Tier Logic FPGA-ASIC

100K LUT Tier Logic FPGA TL1F100 on the left and TL1A100 ASIC on the right

This is the CPU Shack Museum, but occasionally I find a chip thats not really a CPU but is of such interest that I keep it, especially if its novel and relatively unknown.  So today we have a bit of the story of Tier Logic.  Tier Logic set out to make FPGA (Field Programmable Gate Arrays) better, and to make the transition (or choice) between them and ASICs (Application Specific Integrated Circuit) easier.

FPGA’s are great for smaller product runs, they are configurable, and relatively easy to reprogram, designs can easily be updated/tested with no additional cost.  FPGA’s however are large in terms of die area, power budgets, and cost per chip.  ASIC’s on the other hand, take longer to develop (re-spinning silicon every time an error is found) and have a much larger upfront cost, as well as an entirely different tool chain to design with. They are however smaller, use less power, and once the design is finalized, the per unit cost is very low.  This presents a dilemma in design, which should one choose for a project?  What if you didn’t have to choose? What if you could have the flexibility of an FPGA, and the benefits of an ASIC all at once?

It is exactly this that Tier Logic set out to do.  Tier Logic was founded by FPGA process-technology pioneer Raminda Madurawe (from Altera) in 2003 and was led by Doug Laird, a founder of Transmeta (famous for the Crusoe VLIW processors).  For 7 years they worked to design a solution, working in what is known as ‘stealth mode.’  Stealth mode is a way for companies to work quietly, with little to know PR, until they have a product ready to release.  Often the company exists but is completely unknown to outsiders.  This has some definite benefits, there is no constant barrage of having to answer/report to the media and others, and their is less risk of someone seeing what you are doing and trying to beat you to market to it.  Seven years, however, is a very long time to be in stealth mode, and the reason for this is Tier Logic not only was inventing a new style of FPGA/ASIC, they had to develop a new silicon process to make it work.

Read More »

Tags:

Posted in:
CPU of the Day

March 31st, 2019 ~ by admin

CPU of the Day: CS603RMP-200 PowerPC 603r Goes Golden

Chip Supply Inc. CS603RMP-200 – 2005 Production Miltemp PowerPC 603r

The original PowerPC 603 was released way back in 1994, made on a 0.5u process and running at 75MHz.  A year later, the greatly improved PowerPC 603e was released, made on the same process, but supporting speeds of up to 200MHz.  It doubled the L1 caches to 16K each (for Instruction and Data) and introduced some Power Down modes useful for mobile and other low power applications.  A die shrink to 0.5u allowed speeds of up to 300MHz.

The 603e was available in both BGA  and cerquad packages, which worked for most applications.  But what if you wanted something a bit different?  What if your application needed something a bit more robust.  This is where packaging and die specialist companies come into play.  Motorola/IBM had no desire to make short runs of oddball packages and/or dies screened for higher end use.  Other companies however, did…

Motorola MPC603ERX100LN – 2000 vintage PowerPC 603e

Chip Supply Inc. was founded back in 1978 in Orlando, FL  just for this purpose.  Chip Supply provided die testing and packaging services for many different companies.  They also provided a service known as ‘die banking’ and just as the name implies, this involves collection and storing wafers and/or dies for future use.  This helped with end-of-life products especially.  As manufacturers slowed, changed, or stopped production of a device, dies for it could be made available through firms like Chip Supply.

In 1997 Chip Supply Inc. signed an agreement with Motorola giving them access to bare dies and known good dies for the PowerPC 603e, MPC106/7 PCI Bridge, and the MC68000 line.  This allowed Chip Supply to source dies from Motorola, screen them for higher spec (Military and Industrial temp typically).  Motorola had a similar agreement with Thomson-CSF (later this line was acquired by Atmel) who did the same thing, but also made radiation tested parts for space use (notably used on the original Iridium satellite constellation).

16×16 PGA in a 50mm package. Pins are 6mm long (twice as long as a Socket 7 Pentium)

The CS603RMP-200 is a 200MHz PowerPC 603r processor.  The 603r is nearly identical to the 603e, but allows for lower voltages (2.5V) and is made on a 0.29u process.  Chip Supply packaged this in a 16×16 CPGA package that is 50mmx50mm (nearly 2 inches square). It includes a large, gold plated heatspreader thats about the same size as a typical BGA PowerPC 603e.  These use original Motorola dies, upcreened to Military temperature (-55-125C) and tested to run at 200MHz.  The large heatspreader and ceramic package allow for better thermal management, and better mechanical support.  Thermal cycling and vibrations often result in BGA connection failures (a familiar problem on some game consoles in the early 2000’s), something a properly mounted PGA chip is much more tolerant of.

Chip Supply Inc. was acquired by Micross Components in 2010, a company that formed in 1998, and provided the same services with the addition of radiation testing. It appears that this was the end of the line for the entire PowerPC line by Chip Supply, though its likely that custom orders could be fulfilled for sometime after the acquisition.   Someday perhaps we’ll find out what applications the PGA PowerPC 603s were used in.

March 1st, 2019 ~ by admin

CPU of the Day: UTMC UT69R000: The RISC with a Trick

UTMC UT69R000-12WCC 12MHz 16-bit RISC -1992

We have previously covered several MIL-STD-1750A compatible processors as well as the history and design of them.  As a reminder the 1750A standard is an Instruction Set Architecture, specifying exactly what instructions the processor must support, and how it should process interrupts etc.  It is agnostic, meaning it doesn’t care. how that ISA is implemented, a designers can implement the design in CMOS, NMOS, Bipolar, or anything else needed to meet the physical needs, as long as it can process 1750A instructions.

Today we are going to look at the result of that by looking at a processor that ISN’T a 1750A design.  That processor is a 16-bit RISC processor originally made by UTMC (United Technologies Microelectronics Center).  UTMC was based in Colorado Springs, CO, and originally was formed to bring a semiconductor arm to United Technology, including their acquisition of Mostek, which later was sold to Thomson of France. After selling Mostek, UTMC focussed on the military/high reliability marked, making many ASICs and radhard parts including MIL-STD-1553 bus products and 1750A processors.  The UT69R000 was designed in the late 1980’s for use in military and space applications and is a fairly classic RISC design with 20 16-bit registers, a 32-bit Accumulator, a 64K data space and a 1M address space.  Internally it is built around a 32-bit ALU and can process instructions in 2 clock cycles, resulting in 8MIPS at 16MHz.  The 69R000 is built on a 1.5u twin-well CMOS process that is designed to be radiation hardened (this isn’t your normal PC processor afterall).  In 1998 UTMC sold its microelectronics division to Aeroflex, and today, it is part of the English company Cobham.

UTMC UT1750AR – 1990 RISC based 1750A Emulation

UTMC also made a 1750A processor, known as the UT1750AR, and if you might wonder why the ‘R’ is added at the end.  The ‘R’ denotes that this 1750A has a RISC mode available.  If the M1750 pin is tied high, the processor works as a 1750A processor, tied low, it runs in 16-bit RISC mode.  How is this possible? Because the UT1750AR is a UT69R000 processor internally.  Its the same die inside the package, and the pinout is almost the same (internally it may be but that’s hard to tell).  In order for the UT1750AR to work as a 1750A it needs an 8Kx16 external ROM.  This ROM (supplied by UTMC) includes translations from 1750A instructions to RISC macro-ops, not unlike how modern day processors handle x86.  The processor receives a 1750A instruction, passes it to the ROM for translation, and then processes the result in its native RISC instructions.   There is of course a performance penalty, processing code this way results in 1750A code execution rates of 0.8MIPS at 16MHz, a 90% performance hit over the native RISC.  For comparison sake, the Fairchild F9450 processor, also a 1750A compatible CPU, executes around 1.5MIPS at 20MHz (clock for clock, about 30% faster), and thats in a power hungry Bipolar process, so the RISC translation isn’t terrible for most uses.

NASA Aeronomy of Ice in the Mesosphere – Camera powered by RISC

By today’s standards, even of space based processors, the UT69R000 is a bit underpowered, but it still has found wide use in space applications.  Not as a main processor, but as a support processor, usually supporting equipment that needs to be always on, and always ready.  One of the more famous mission the UT69R000 served on was powering the twin uplink computers for the DAWN asteroid mission (which only this year ended).  It was also used on various instrumentation on the now retired Space Shuttles. The CPU also powered the camera system on the (also retired) Earth Observing-1 Satellite, taking stellar pictures of our planet for 16 years from 2000-2017.  Another user is the NASA AIM satellite that explores clouds at the edge of space, originally designed to last a couple years, its mission which started in 2007 is still going.  The

JAXA/ESA Hinode SOLAR-B Observatory

cameras providing the pretty pictures are powered by the UT69R000.  A JAXA/ESA mission known as SOLAR-B/Hinode is also still flying and running a Sun observing telescope powered by the little RISC processor.

There are many many more missions and uses of the UT69R000, finding them all is a bit tricky, as rarely does a processor like this get any of the press, its almost always the Command/Data Processor, these days things like the BAE RAD750, and LEON SPARC processors, but for many things in space, and on Earth, 16-bits its all the RISC you need.

January 24th, 2019 ~ by admin

Intel Everest Goes to Auction

Last summer we wrote about the Intel Everest series of high end CPU’s.  These are processors which Intel makes for very specific customers (in this case High Frequency stock trading).  They often have very little official information about them, and are sold at prices around $20,000 each. The latest in the series is the Intel Core i9-9990XE, with a max Turbo Frequency of 5.1GHz.  According to Anandtech, these will be auctioned off to the highest bidder.  These chips are a 14-core processor dissipating 255W, so will require rather good cooling, motherboard and Power Supply Support.  The chips will be auctioned to ‘select OEM’s’ once per quarter throughout 2019.  Intel isn’t likely deliberately making these chips scarce to increase the price, they are rather very rare speed bins for chips to attain.  Out of thousands of chip’s tested, only a few will pass screening at this level of performance.  These typically come from the center of a wafer (defects typically increase towards the edge of a wafer).  It will be interesting to see what prices these attain, but then again, we may never know.

December 29th, 2018 ~ by admin

The End is Near (of the year) – A Look Back at Y2K

AMD Y2Kids Career Day – K6-2 Custom Painted 

Think back 19 years, the year is 1999 and in just a few days the world is apparently coming to an end due to programmers of the 60’s and 70’s deciding to save precious memory and use 2-digits for the year instead of 4.  Or perhaps they just assumed that in 30-40 years we really wouldn’t be using the same systems. Either way the world (and by world we mean mainly the media) was prepared to go dark as everything technology driven ground to a halt as the clocks struck midnight.  Kids pondered if this would mean an extended holiday break, while parents wondered if they would still have a job, or money in their computer controlled checking account.

Thankfully (though perhaps looking back that is becoming murky to some) it was a complete non-even, life, and technology continued at a record pace. And who would want to miss it? The GHz war between AMD and Intel was neck and neck at the turn of the millennium, with AMD set to win it by a few days.  This was the age of the Pentium 3, the Athlon and the K6-2.  Technology was glamorous and some of its downsides seen today were relegated to sci fi movies.  AMD and other companies held job fairs to acquire new talent, and also hosted Career Days for younger kids to see what went on in the exciting tech industry.  This specially painted AMD K6-2 CPU was likely handed out during such an event, probably either in Austin, TX (where AMD had a large fab) or Santa Clara, CA.  Its a NTK made package with a AMD package # 26351, the standard from 1998-2000 and used for most all late K6-2 CPUs. The child who likely would have received this, probably a middle schooler at the time would now be around 30, who knows how such an event affected them but it would be neat if they ended up working at AMD (or Globalfoundries) or at the very least sing an AMD powered computer.