Archive for the 'CPU of the Day' Category

March 12th, 2017 ~ by admin

When Intel Runs out of Chips…..

Intel D80130-3 OSP – Engineering Sample – Early 1982

A seemingly impossible occurrence today, but something that Intel has faced in the past.  It is common for customers to need chips that are no longer in production, either for repair of legacy systems, or to keep an old but reliable design in production.  Typically these parts can be sourced on the secondary market, or from End-of-Life suppliers such as REI, or InnovASIC.  But what happens when Intel themselves needs a chip that they previously made, but no longer do?

Such was the case with the 80130 Operating System Processor.  The 80130 was a co-processor designed in 1981, to make use of Intel’s high-density ROM capabilities.  The 80130 contained 16K of ROM, 3 timers (compatible with 8254), an interrupt controller (similar to the 8259), and a baud-rate generator.  It was capable of bus management and control and could directly control an 8087 FPU as well.  These are designed to work with the 8086/88 and 80186/188 processors.  The 16K of ROM was coded with 35 Operating System primitives (a subset actually of the Intel iRMX86 RTOS (Real Time Operating System).  This firmware allowed easier support for the constructs typically used in a multitasking OS.  Essentially the 80130 extended the instruction set of the x86 to include higher level OS functions.

Intel D80130-2 – 1983 – Production version (though datasheets continued to be marked ‘Preliminary’ though its entire life)

The original version, called (for no known reason) the 80130-3 was released in engineering sample versions only.  It could run at up to 8MHz allowing it to work with any of the x86 processors of the time.  After some small timing adjustments, the 80130 was released to production as the 80130-2, still keeping with the 8MHz max.  Later references show a 80130 at 5MHz as well as the 8MHz -2 part.  However, the 5MHz part has not been seen (as of this writing) and is likely to exist only in datasheets.

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February 26th, 2017 ~ by admin

Aeroflex UT80CRH196KDS – The MCS-196 Goes to Space

Aeroflex 5962F0252301VXA = UT80CRH196KDS
F = 3×105 Rad
01 = Mil Temp (-55C-125C)
V = Class V

The MCS-196 is the second generation of Intel’s MCS-96 family of 16-bit processors.  These are a control oriented processor originally developed between Ford Electronics, and Intel in 1980 as the 8060/8061 and used for over a decade in Ford engine computers.  They include such things as timers, ADC’s, high-speed I/O and PWM outputs.  This makes them well suited for forming the basis of applications requiring control of mechanical components (such as Motors, servos, etc).  The 196KD is a 20MHz CMOS device with 1000 bytes of on die scratch pad SRAM. The UT80CRH196KDS (unqualified/not tested for radiation) is priced at $1895.00 in quantities of 5,000-10,000 pieces (in 2002). Fully qualified ones will of course cost a lot more. The KDS is a drop in replacement for the previous KD version, which only supported doses of 100krads.

This obviously lends itself to automotive applications, hard disk control, printers, and industrial applications.  There is however, another application they have found wide spread use in, spacecraft.  Spacecraft are not all to different from a car in the amount of mechanical systems that must be interfaced to the computer controls.  The difference however, is that unlike your car, spacecraft electronics must work, always.  If a car fails, its an annoyance, if a spacecraft fails, it has the potential to cost millions of dollars, not to mention the loss of a mission.  If that spacecraft happens to be the launch vehicle, a failure can directly result in a loss of life.

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February 19th, 2017 ~ by admin

Milandr K1986VE91T – The ARM of Russia

Milandr K1986VE91T – 80MHz ARM Cortex-M3

In the early 1990’s a Milandr was formed in Zelenograd, Russia (just a short distance to the NW of Moscow), the silicon valley of Russia, home to the Angstrem, and Micron IC design houses. They are a fabless company, though with their own packaging/test facilities, specializing in high reliability metal/ceramic packages. Most of their products are fab’d in Germany, by X-Fab.  X-Fab was formed in part, from the remains of the Soviet/E. German era VEB Mikroelektronik Karl Marx, in Erfurt Germany, also known as FWE/MME and later Thesys.  In Soviet times it wasn’t uncommon for Soviet companies to use dies produced by FWE in their own packages, so this bit of legacy continues today.

The K1986VE91T is one of Milandr’s top end products, it is an 80MHz ARM Cortex-M3 based processor, and likely one of the largest, if not the largest, Cortex-M3 made.  It is made on a 180nm process and includes 32K RAM, 128K FlashROM, 96 USER I/O, USB, 2 UART and 12-bit DAC/ADC.  Judging by the die, the processor was built with standard licensed blocks, very common for such designs.  Milandr licensed the ARM Cortex-M3 itself in December of 2008, for use mainly in automotive and industrial applications. Milandr is also the very first Russian company to license and use an ARM core.

Analog Devices ADUCM322BBCZ ARM Cortex-M3 80MHz – Same basic core, but in a very much less appealing package

The package, however, is completely unique.  It is a 132 pin CQFP package. There are 33 gold leads on each side of the white ceramic package.  Each row is actually 2 staggered rows, the offset allows the finer lead pitch, and still room to bond the leads to the top of the package.  Soviet processors were often delivered in the most stunning of packages and 25 years later, Milandr keeps that tradition alive.

Each of these processors came with a brief datasheet, complete with inspection stamps for the processor. It is all in Russian, but check it out here.

Milandr made several variations of the Cortex-M3, including the VE92 and VE93 which are internally identical, but with much less I/O available owing to there smaller 64 pin and 48 pin packages respectively. Milandr also made a copy of the PIC17 processor that we covered last year.

A version of the K1986VExx continues to be made by Milandr, but renamed to the MDR32F9Qx.  It continues to have the same basic core, but in a 144 pin package, allowing even greater I/O support.

 

January 15th, 2017 ~ by admin

HP 1000 A700 Processor: Rise of the Phoenix

HP 12152-60002 A700 Phoenix Processor – 4x AMD AM2903 (1820-2377)

The Lighting processors of the HP A600 and A600+ were good performing for 1982.  They filled the entry and mid range slots of the HP 1000 A Series quite well.  The additional floating point support of the A600+ in 1984 helped considerably as well, but what was needed for truly better performance on the high end was hardware math support.  While the HP A600 took only 9 months to design and release, the A700, released at the same time, took somewhat longer.  The A600 was based on the AMD 2901, which had been released way back in 1975.  The A700 Phoenix was based on its successor, the AM2903.  The 2903 added a few important features to the bit-slicer.  Hardware multiply and divide support,support for more registers, and easier ways to access them, and parity generation.  This is why the A700 took longer to design, the A600 design was begun half way through the A700 to fill the lower end, where the features of the 2903 wouldn’t be as missed.

The A700 performs at the same 1 MIPS as the A600 but supports 205 standard instructions (compared to 182 for the A600 and 239 for the A600+).  It adds more register reference instructions, dynamic  mapping, I/O and more math based instructions.  Cycle time is actually slightly slower, 250ns compared to 227ns for the A600 but the 2903 allows more efficiency making up for the difference.  A typical FMP instruction take 13.75-25.25 microseconds compared to 16.6-26.6 on the 2901 powered A600.  This is a direct result of the hardware multiply hardware included in the 2903.  The A600+, with its faster 2901C’s completes the same instruction in 17-21.1 microseconds, FASTER then the A700. But the A700 has a trick up its sleeve….

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January 6th, 2017 ~ by admin

HP 1000 A600: The Lighting Processor

HP A600+ Processor Board. 4x AMD AM2901CDC (1820-3117) 1x AMD AM2904DC and 1x AMD AM2910 (1820-2378). Some versions used 2901’s from National Semiconductor.

In the early 1960’s HP was exploring connecting computers to its various instruments, for control, monitoring, and logging.  The DEC PDP-8 had come out in 1965 as perhaps the first mini-computer and could be used to control HP’s instrument’s.  However, HP determined that it would actually be easier, and faster to design and build their own computers rather than work with DEC.  DEC probably didn’t see HP’s interest as important enough to make it easy (some interfacing for I/O etc would have to be done).  It worked out well for HP however, as this pushed them into an entirely new, and emerging market.

In 1966 HP released the 16-bit HP 2100 (later to be renamed the HP 1000 series).  It was a design that had begun under Union Carbide’s Data Systems Inc, a company HP had recently acquired.  This gave HP a head start, and allowed them to evolve the design to meet their needs (at the time mostly to control instruments).  When released it included not only the hardware but a completely function software suite as well, including a FORTRAN compiler.  They initially ran with a 10MHz clock and a 1.6usec memory cycle time.

Throughout the 1970’s the design evolved, and would lead to many computers.  The 98xx desktop systems using HP’s NMOS BPC Hybrid processor were based on the HP 1000 series.  The design was a fairly simple accumulator based architecture with 2 16-bit accumulators (A and B) and a 15-bit PC and 68-base instructions.  The first version was directly programmed but all subsequent versions were microprogrammed, making alterations and additions to the instruction set much easier, a feature that became important in keeping the HP 1000 around.

The A series were the HP 1000’s of the 1980’s.  Development began around 1980 and the first computers, the A600 and A700, were released in 1982.  These were some of the first LSI based processors for the line.  THe A600 processor was called the ‘Lightning.’  The name “Lightning” came from the Mark Twain quote “Thunder is good, thunder is great, but it is lightning that does all the work.” “Thunder” was a reference to the PDP 11/23, one of DEC’s newer machines at the time.  HP had went from considering using DEC’s computers to run instruments, to the 4th largest maker of such computers in only a decade.  Certainly a fact not lost on either company.

The A600 is an interesting design, it is of course microprogrammed, and is based on AMD AM2901B bit-slice processors, supported by a 2910 microsequencer, and the 2904 status/shift control unit.  The rest of the board is Schottky TTL, PALs, FPLAs. and ROMs.  Each HP 1000 instruction is microcoded into a 56-bit instruction for controlling the 2901’s 2904 and 2910.  These 56-bit instructions directly operation on the processor.  Certain bits interface with certain parts of each chip, so they are directly executed.

A600 – 56-bit microinstruction word directly operates on the hardware (click for LARGE version)

A series of PAL’s contain the microcoding, allowing for easy updating (at the time).  A standard A600 executed 182 standard HP 1000 instructions.  It could do so at a rate of 1 MIPS, with a cycle time of 227 nanoseconds.

Each 2901 is a 4-bit slice processor, and contains 4-bit registers and ALU’s.  The HP 1000 A and B registers are mapped directly to the R0 and R1 registers of the 2901’s and the Program counter resides in R15.  The PAL’s determine what HP 1000 instruction is being executed, and decode it into the proper 2901 assembly code, building the 56-bit instruction word.  This is one of the best examples of how the AMD 2901 (and other bit slicers) were designed to be used.  The end user has no idea, or need to know what is executing their HP 1000 code.  Its is decoded and send to the bit slicers for processing which then return the results to the proper place.  If new functions are needed a new processor does not need to be designed, simply add additional PAL code to decode the new instructions.  And that is exactly what HP did….

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November 26th, 2016 ~ by admin

HP 3000 Series 33: 16-bits of Sapphire

HP 3000 Series 33 - 16-bits 11MHz. They were integrated into the desk, with a 20MB hard drive on the left, and the computer on the right (with a 1.2MB 8" Floppy Drive)

HP 3000 Series 33 – 16-bits 11MHz. They were integrated into the desk, with a 20MB hard drive on the left, and the computer on the right (with a 1.2MB 8″ Floppy Drive)

In 1972 HP introduced the HP 3000 line of minicomputers.  Mini of course meaning they didn’t take up the entire room.  They competed against the likes of the DEC PDP-11 and the TI-990.  Original called the System/3000 (apparently to compare favorably to the IBM System/360) they were renamed the HP 3000.  These were 16-bit computers employing a stack based design,  They had no general purpose registers, all operations operated directly on one of several stacks.  The first models were designed using bipolar discrete logic and ROM for the microcoding.  This allowed for good performance but was expensive and large.  Just the processor for the high end Series III of 1978 was 9 boards.

The Series 33 (and the smaller series 30) were to be cost reduced versions, to slot in between the high end Series III and the newly introduced HP 300 microcomputer.  In order to do this those 9 boards for the processor needed to be greatly simplified.  HP engineers decided to use a processor they had already, the CPU from the HP 300 Amigo.  The HP Amigo was a bit of a disaster for HP, after 5 years of development, including

1AB4-6003 RALU -Silicon on Sapphire - 8000 Transistors

1AB4-6003 RALU -Silicon on Sapphire – 8000 Transistors

designing an entirely new processor it was a failure in the market, suffering from management and politics more then from a technical standpoint (it was not file system compatible with the 3000 line and that caused some concerns).  After being released in 1978 it made only around $15 million in sales and was canceled after a short time.

Part of that 5 year development was for its 16-bit VLSI processor.  In order to get the speed needed for the HP 300 and at a low price, the pressor needed to be a VLSI design (a few chips rather then a few boards).  In order to fit in a smaller pedestal cabinet it needed to energy efficient and heat efficient as well.  HP’s engineers decided to use a Silicon On Sapphire (SoS) CMOS design, a process HP had some great experience with in the MC2 processor.  SoS is a form of Silicon on Insulator, a manufacturing method that is very common in today’s IC’s (using Silicon Dioxide).  Instead of an IC being made on a pure silicon wafer, the silicon is deposited on a wafer of sapphire.  Sapphire is an excellent insulator which wels reduce leakage currents, as well as spurious currents from such things as radiation.  Radiation tolerance is perhaps what SoS became known for most, but its low power performance was what HP was after in the 1970’s.

Die shot of the RALU with labels.

Die shot of the RALU with labels.

The processor for the HP 300 was designed into 3 separate IC’s, totaling 20,000 transistors (some documentation says 25,000) and running at a clock of 11MHz.  The processor control unit (PCU 1AB2-6003) chip generates microinstruction addresses that control the other two chips: the register, address, skip, and special (RASS 1AB3-6003) chip and the register, arithmetic, and logic unit (RALU 1AB4-6003) chip.

The PCU contains 5000 transistors and handles the microsequencing, clock generation, and a sub-routine save stack.  Clock generation is interesting as its single phase, and variable.  The PCU can lengthen or shorten the clock period as needed.  If a memory operation needs longer to complete the PCU simply holds the lock period longer.  Data path functions are handled by the RASS and RALU chips.  The RASS contains about 7000 transistors and contains a register file for the second operand to the RALU as well as address generation and skip logic.  The largest of the chips is the RALU.  It handles all of the standard ALU functions as well as hardware multiply/divide.  It also contains 16 registers: 8 general purpose registers, and 8 for address storage.  Together these three chips form the CPU of the HP 300 and consume only 1Watt of power.  The processor is a microcoded design so the actually instruction set resides in ROM, in this case on a separate board.  In the case of the HP 300 this also allowed the I/O processor duties to be microcoded into the general processor, eliminating another subsystem.

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November 5th, 2016 ~ by admin

GRAPE-6 Processor: A Gravitational Force of Reckoning

GRAPE-6 Processor - 90MHz

GRAPE-6 Processor – 90MHz -2000

Understanding the movements of the stars has been on mankinds mind probably since we first stared into the sky.  Through the ages we can predict where a star or planet will be in the sky in the next few months, years, even hundreds of years, but to be able to predict the exact orbital details for ALL time is rather more tricky.

This helps understand how planetary systems form, and the conditions that make that possible.  It allows us to see what happens when two massive black holes pass each other by, will the merge? will they orbit? will one go rogue?  These are interactions that take millions of years, and thus we need to calculate the gravitational forces very accurately. This isnt a terribly hard problem for two bodies, and is doable for three with little fuss, but for numbers of bodies greater then that, the calculations grow rapidly, on the order of N2/2.

In the late 1980’s Tokyo University began work on developing a computer to calculate these forces.  Every gravitational force had to be be calculated with its effects on every other body in the system.  These results were then fed to a commodity computer for summation and final results.  This made the Tokyo project a sort of Gravity co-processor, or as they called it a Gravity Pipeline, GRAPE for short.  The GRAPE would do the main calculations and feed its results to another computer.

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October 20th, 2016 ~ by admin

Processors to Emulate Processors: The Palladium II

Cadence Palladium II Processor MCM 1536 cores - 128MB GDDR - Manufactured by IBM

Cadence Palladium II Processor MCM 1536 cores – 128MB GDDR – Manufactured by IBM

Several years ago we posted an unusual MCM that’s purpose was a mystery.  It was clearly made by IBM and clearly high end.  While researching another mystery IBM MCM both of their identities came to light.  The original MCM is an emulation processor from a Cadence Palladium Emulator/Accelerator system.

In the 1990’s IBM had been working on technology to make emulating hardware/software designs more efficient as such designs got more complicated.  At the time it was most common to emulate a system in an FPGA for testing, but as designs grew more complex this became a slower and slower process.  IBM developed the idea of an emulation processor.  This was to be known as CoBALT (Concurrent Broadcast Array Logic Technology).  It was licensed to a company called QuickTurn in 1996.  At its heart the QuickTurn CoBALT was a massively parallel array of boolean logic processors.  Boolean processors are similar to a normal processor

Here is a flipped (and very rough) die from a Palladium II. You can make out the very repeating design of the 768 boolean processors.

Here is a flipped (and very rough) die from a Palladium II. You can make out the very repeating design of the 768 boolean processors.

but only handle boolean data, logic functions such as AND, OR, XOR, etc.  Perhaps the most well known, is the boolean sub-processor that Intel built into the 8051, it excelled at bit manipulation.  The same applies for the emulation processors in CoBALT.  Each boolean processor has at its heart a LUT (Look Up Table), with 8-bits to encode the logic function (resulting in 256 possible logic function outputs) and the 3 gate inputs serving as an index into the LUT, as well as the associated control logic, networking logic, etc.

A target design is compiled and emulated by the CoBALT system.  The compiling is the tricky part, the entire design is broken down into 3-input logic gates, allowing the emulator to emulate any design.  Each processor element can handle one logic function, or act as a memory cell (as many designs obviously include memory).  The CoBALT had 65 processors per chip, and 65 chips per board, with a system supporting up to 8 boards.  This 33,280 processor system could compile 2 Million gates/Hour.  The CoBALT plus sped this up a bit and supported 16 boards, doubling capacity and added on board memory.

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October 16th, 2016 ~ by admin

Signetics 2650: An IBM on a Chip

Signetics 2650I - Original Version from May of 1976

Signetics 2650I – Original Version from May of 1976

The Signetics 2650 processor has always been described as ‘very mini-computer like’ and for good reason, it truly is very minicomputer like in design.  It is an 8-bit processor released in July of 1975 made on an NMOS process.  The 2650 has a 15-bit address bus (the upper bit (16) is reserved for specifying indirect addressing) allowing addressing of up to 32K of memory.  It has 7 registers, R0, which is used as an accumulator, as well as 2 banks of 3 8-bit registers accessed.  The 2650 supports 8 different addressing modes, including direct, and indirect with autoincrement/decrement.  Its clearly a mini-computer design and there is a reason for that, it was based on one.

The 2650 is very closely based on the IBM 1130 mini-computer released in 1965.  Both use 15-bit addressing, many addressing modes, and a set of 3 registers (Signetics added support for 2 banks of 3,  The Signetics 2650 is often noted for its novel use of a 16-bit PSW status register, but this too is from the 1130, which used a 16-bit Device Status Register for talking with various I/O components.  So why would Signetics base a processor released in 1975 on a 1965 mini-computer?

Because the 2650 was not designed long before it was released.  J. Kessler  was hired by Signetics in 1972 in part to help design an 8-bit processor.  Kessler was hired by Jack Curtis, (Of Write Only Memory fame) from…IBM. Kessler designed the architecture very similar to the IBM 1130 and Kent Andreas did the silicon layout.  The design contains 576 bits of ROM (microcode mainly), ~250 bits of RAM (for registers, stack, etc) and about 900 gates for logic.  Clock speed was 1.25MHz (2MHz on the -1 version) on a ion implanted NMOS process, very good for 1972 (this was as fast as the fastest IBM 1130 made), but Signetics was tied up working with Dolby Labs on audio products (noise canceling etc) and didn’t have the resources (or perhaps the desire) to do both, so the 2650 was pushed back to 1975.  In 1972 the IBM 1130 it was inspired by was still being made.  If the 2650 had been released in 1972 it would have had the Intel 4004 and 8008 as competition, both of which were not easy to use, and had complex power supply and clocking requirements.  The 2650 needed a 5V supply, and a simple TTL single phase clock.

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October 4th, 2016 ~ by admin

Testing all the ARMs

ARM946E on a Chartered Semiconductor 0.18u Process

ARM946E on a Chartered Semiconductor 0.18u Process

ARM is one of the most popular RISC cores used today, and has been for over a decade now.  ARM is an IP company. They license processor designs/architectures for others to use, but do not actually manufacturer the processors themselves….or do they?

ARM offers a variety of cores, and licenses them in a variety of different ways.  There are, in general, three main ways to get an ARM design.  Larger companies with may resources (such as Apple, Broadcom, or Qualcomm) will purchase an ARM architecture license.  This isn’t specific to any ARM core in particular (such as say a ARM946) but the entire ARM architecture, allowing these companies to design their own ARM processors from the ground up.  This takes a lot of resources and talent that many companies lack.

Second, ARM offers RTL (Register Transfer Level) processor models, these are provided in a hardware programming language such as VHDL or Verilog.  They can be dropped into a design along with other IP blocks (memory, graphics, etc) and wrapped with whatever a company needs.  This is a fairly common method, and typically the lest expensive.  It does require more work and testing though.  Designing a chip is only part of the process. Once it’s designed it still must be fab’d.

ARM7EJ-S on a TSMC 0.18u Process. Wafer #25 from June 2003

ARM7EJ-S on a TSMC 0.18u Process. Wafer #25 from June 2003

ARM also offers ARM models that are transistor level designs, pre-tested on various fab processes.  Pre-tested means exactly what it sounds like. ARM designed, built and had them manufactured, fixing any problems, and thus giving the ability to say this core will run at this speed on this fab’s process.  Testing and validation may often go as far as testing a particular fab’s particular process, in a particular package.  Its more work, and thus cost more, but these make for drop in ARM cores. Want to use a ARM946 core, on a TSMC 0.18u process in a lead free Amkor BGA package? Yah ARM’s tested that and can provide you with a design they know is compatible.  This allows extremely fast turn around from concept, to design to silicon.

In the below picture (click to enlarge) you can see a large variety of ARM cores from the early 2000’s. They span ARM7, ARM9, ARM10 and ARM11 designs.  Each is marked with info as to what exactly it is.  The core name, the revision (such as r2p0, meaning major revision 2, pass/subversion 0) as well as the Fab (TSMC, UMC, SMIC, Chartered) and the design node (all of these are either 0.18 or 0.13u processors).

21 Various ARM design tet chips from TSMC, UMC, Charted, covering many ARM cores.

21 Various ARM design tet chips from TSMC, UMC, Charted, covering many ARM cores.

Also noted on some is the exact wafer the die was cut from, this is typical on VERY early production tests, usually first run silicon, so they can identify any physical/manufacturing defects easier.  Some design modifications have little to do with the processor itself, but are done to increase yields on a given process/node.

ARM926EJ on a UMC 0.13u Process. THe package has a removable die cover.  Note the large die, thought he processor core itself is very small (its in the upper left)

ARM926EJ on a UMC 0.13u Process. 

Package type (in this case most are Amkor BGA) and other features are noted.  Many say ‘ETM’ which is ARM’s Embedded Trace Macrocell, a debugging tool that allows instruction and date traces of an in operation core, very useful for debugging. ARM offers ETM for each of their processor types (ETM9 for example covers all ARM9 type cores) and itself has a revision number as well.

Some of these chips come in an interesting BGA package. The package has a removable die cover for inspection/testing (and possibly modification). Note the large die in the ARM926EJ on the left, though the processor core itself is very small (its in the upper left only a few square mm).  This is done to facilitate bonding into the package, In this type of package there wouldn’t be any way to connect all the bonding wires to the very tiny ARM core, so the die has a lot of ‘wasted’ space on it.

So does ARM make processors? Yup! but only for internal use, to help develop the best possible IP for their clients.

 

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