DEC’s 32-bit VAX architecture saw many implementations since its introduction in 1977. Early implementations were all multi-chip, but as technology improved the VAX architecture could be implemented (at least partially) on a single VLSI chip. The first implementation on a single chip was the MicroVAX II released in 1985. It contained 125,000 transistors, made on a 3 micron NMOS (DEC proprietary ‘ZMOS’) process and ran at 5MHz (200ns cycle time).
In 1987 DEC released the CVAX, the second generation VAX on VLSI. The CVAX was made on DEC’s first CMOS process, a 2 micron design using 175,000 transistors and clocked from 10-12.5 MHz (80-10ns cycle time). The input clock was a four-phase overlapping clock (so input frequency was 4x the cycle time, or 40-50MHz). Performance was 2.5-3 times better then the MicroVAX II. About half the gain was from process improvement (increased clock speed), while the rest was from architectural changes (mainly pipelining).
As the CVAX (and its successor the CVAX+) were released the next generation was already being designed by DEC. This was to be Rigel. Rigel has a 6-stage pipeline, and was made on a 2 micron CMOS process and the CPU contained 320,000 transistors, 140k of which were for logic, while the remaining 180k were for memory (cache). The separate FPU chip contained an additional 135,000 transistors. After some early teething pains on the new CMOS process, where yields were almost non-existent, the process finally was refined enough to make commercial samples by late 1988. The target speed for Rigel was a 40ns cycle (25 MHz clock). This would give the Rigel a 6-8x performance gain over CVAX. 2X of this was from the process shrink (and doubling of clock speed) while 3X was from the improved pipelining. The remainder was due to increased memory performance, not the least of which was due to Rigels 2KB of on chip cache.
Rigel, however, had other plans…