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September 9th, 2020 ~ by admin

Finding the Limits of the Socket 8

Socket 8 processors have something magical and I really enjoy working with them. Earlier I wrote about them more than once and it would seem that everything has already been said, but in this article you will find out which PC configuration is truly the fastest on Socket 8, although it never existed in reality. I just gave this platform what it never had, it’s like giving the first representatives of the Skylake processor architecture, which was released back in 2015, DDR5 and PCI-Express 4.0 today.

Before starting another fascinating story about Socket 8 and the processors that were installed there, I will give links to my previous experiments:

Chapter 2: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997
and what got us started…
Part 1: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997

As you can see, my close acquaintance with this socket has existed for a long time and over the past few years we have clearly managed to make friends. It would seem that all Socket 8 processors have been studied and tested in various configurations, including an insane configuration of six processors in such a monster as the ALR Revolution 6×6. But quite recently I got my hands on a motherboard made by ASUS, which gave me the opportunity to take a fresh look at the use of processors and the performance they are able to give in a newer platform.

What is this board and what chipset is it based on? To name the heroine of today’s article, I will first dwell on the main chipsets for Socket 8 processors. The first chipsets for Intel Pentium Pro processors appeared in November of 1995, 25 years ago. Already at that time, they understood that the future was behind the parallel execution of various tasks. The Intel 450KX chipset, codenamed “Mars”, was introduced for workstations, and the Intel 450GX “Orion” for servers. Mars allowed for dual-processor configurations, and the Orion officially supported up to four physical processors. Although on the example of the super-server ALR Revolution 6×6, which is based on Intel 450GX, the number of processors could have been much larger and could easily double the official figure.

Nowadays the term chipset is often associated with a single chip located on the motherboard, but when applied to the first chipsets for Intel Pentium Pro processors, we are dealing with the physical seven chips that made up the “number of special chips” or “chipset.” These chipsets supported slow FPM DRAM standard RAM, the server GX chipset could operate with 4 GB of such memory, while the KX “was content” with 1 GB support (Intel figuring a workstations needed less RAM then a server). By the standards of the second half of the 90s, these were immense volumes of RAM

In May 1996, a more progressive chipset appeared – Intel 440FX “Natoma”, which quickly began to replace older system logic sets. Intel 440FX itself already consisted of a pair of microcircuits, support for SMP, faster EDO / BEDO DRAM memory types along with the outdated FPM DRAM (though limited to 1GB max of RAM), a new version (2.1) of the PCI bus standard, as well as support for Intel Pentium-II processors were announced.

Most motherboards based on the Intel 440FX “Natoma” chipset have a physical design in the form of a Socket, where the processor was installed, but there were exceptions with a few using the new Slot 1 slot, where the first Pentium-II and Pentium Pro were installed through special slot adapters. A good example is the ASUS KN97-X motherboard with the included Socket 8->Slot 1 adapter called the ASUS C-P6S1.

ASUS KN97-X motherboard with ASUS C-P6S1 slocket adapter

Each manufacturer of such slot motherboards produced their own slot adapters, but due to their small circulation, finding them is now problematic. Socket 8 processors feel good in such adapters and the presence of a more modern infrastructure of such motherboards obviously contributes to an increase in performance. But Intel, having released the Intel 440FX chipset, decided to stop further support for its Socket 8 processors, although it could really have extended their life cycle.  Why just sell people a new motherboard chipset, when you cold ALSO force them to buy a new CPU to go in it?

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Boards and Systems

August 20th, 2020 ~ by admin

HP NanoProcessor Mask Set

Since we have a complete, and very early mask set of the HP NanoProcessor (donated by Mr Bower, thank you) it seemed fitting to scan them in (tricky at 600 dpi and 6 scans each (they are around 40x60cm) then I sent them over (500MB) my friend Antoine Bercovici in France to stitch and clean, as well as remove the background.  THat allowed this cool animation of the mask being built.
These are made from a set of 100X Mylar masks

Here you can see how the 6 different mask layers are built up.  The last mask layer (black) is the bonding pads
Each individual layer is also shown, some are very simple, while others contain a lot more.

In the lower left corner of the masks you can see their layer number 1B 2A 3A…etc

You can see the original HP part number on the mask 9-4332A as well as ‘GLB’  GLB is a composition of the initials of the two designers of the chip: George Latham and Larry Bower.

Here is a larger version as well: HP NanoProcessor Mask Set

 

 

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CPU of the Day

August 9th, 2020 ~ by admin

The Forgotten Ones: HP Nanoprocessor

Original Nanoprocessor prototypes from 1974-75. Note hand written wafer number, open die cover and early part number (94332)

Back in the 1970’s the Loveland Instrument Division (LID) of HP in Colorado, USA was the forefront of much of HP’s computing innovation.  HP was a leader, and often THE leader in computerized instrumentation in the early 1970’s.  From things like calculators, to O-scopes to desktop computers like the 9825 and 9845 series.  HP made their own processors for most all of these products.  The early computers were based on the 16-bit Hybrid processor we talked about before.  At around the same time, in 1974, the HP LID realized they needed another processor, a control oriented processor that was programmable, and could be used to control the various hardware systems they were building.  This didn’t need to be a beast like the 16-bit Hybrids, but something simpler, inexpensive, and very fast, it would interface and control things like HPIB cards, printers, and the like.  The task of designing such a processor fell to Larry Bower.

The result was a Control Oriented Processor called the HP nanoprocessor.  Internally it was given the identifier 94332 (or 9-4332), not the most elegant name, but its what was on the original prototypes and die.   The goal was to use HP’s original 7-micron NMOS process (rather then the new 5-micron NMOS-II process) to help save costs and get it into production quickly.

Nanoprocessor Features – Note the speed has been ‘adjusted’

 

The original design goal was a 5MHz clock rate and instructions that would execute in 2 cycles (400ns).  The early datasheets have this crossed out and replaced with 4MHz and 500ns, yields at 5MHz must not have been high enough, and 4MHz was plenty.

Handwritten Block diagram

 

The Nanoprocessor is interesting as it is specifically NOT an arithmetic oriented processor, in fact, it doesn’t even support arithmetic.  It has 42 8-bit instructions, centered around control logic.  These are supported by 16 8-bit registers, an 8-bit Accumulator and an 11-bit Program Counter.  Interface to the external world is via an 11-bit address bus, 8-bit Data bus and a 7-bit ‘Direct Control’ bus which functions as an I/O bus.  The nanoprocessor supports both external vectored interrupts and subroutines.  The instructions support the ability to test, set and clear each bit in the accumulator, as well as comparisons, increments/decrements (both binary and BCD), and complements.

Here is one mask (Mask 5 of 6) for the prototype Nanoprocessor. You can see its simplicity.  On the bottom of the mask you can see the 11-bit address buffers and Program Counter

2.66MHz 1820-1691 – note the -5V Bias Voltage marked on it

The Nanoprocessor required a simple TTL clock, and 3 power supplies, a +12 and +5VDC for the logic and a -2VDC to -5VDC back gate bias voltage.  This bias voltage was dependent on manufacturing variables so was not always the same chip to chip (the goal would be -5VDC).  Each chip was tested the and voltage was hand written on the chip.  The voltage was then set by a single resistor on the PCB.  Swapping out a Nanoprocessor meant you needed to make sure this bias voltage was set correctly.

If you needed support for an ALU you could add one externally (likely with a pair of ‘181 series TTL).  Even with an external ALU the Nanoprocessor was very fast.   The projected cost of a Nanoprocessor in 1974 was $15 (or $22 with an ALU),  In late 1975 this was $18 for the 4MHz version  (1820-1692) and $13 for the slower 2.66MHz version (1820-1691).

At the time of its development in 1974-1975 the Motorola 6800 had just been announced. The 6800 was an 8-bit processor as well, made on a NMOS process, and had a maximum clock rate of 1MHz.  The initial cost of the 6800 was $360, dropping to $175, then $69 with the release of the 6502 from MOS.  By 1976 the 6800 was only $36, but this is still double what a Nanoprocessor cost

 

An early ‘slide deck’ (the paper version equivalent) from December 1974 sets out the What Why and How of the Nanoprocessor.  The total cost of its development was projected to be only $250,000 (around $1 million in 2020 USD).  The paper compares the performance of the Nanoprocessor to that of the 6800.  The comparisons are pretty amazing.

Interrupted Count Benchmark

For control processing interrupt response time is very important, the Nanoprocessor can handle interrupts in a max of 715ns, compare that to 12usec for the 6800.   The clock rate of the Nanoprocessor is 4 times faster but the efficiency of its interrupts and instructions are what really provides the difference here.

The clock rate difference (1MHz vs 4) really shows here, but the Nanoprocessor is also executed 3 times the instructions to do the same task, and still is faster.

Even using an external ALU compared to the Motorola’s internal ALU, the nanoprocessor is better then twice as fast (thanks here to its much higher clock frequency)

Full Handshake Data Transfer. Interfacing to the outside world was the main driver of the Nanoprocessor. Here we see that it can ‘talk’ to other devices much faster then the 6800

All instructions on the Nanoprocessor take 500ns to execute compared to the 1-10u for the 6800.

Today we do benchmarks based on framerates in games, or render times, but you can see that benchmarks were even important back then.  How fast a processor could handle things determined how fast the printer could be, or how fast it could handle external data coming in.  It’s no wonder that the Nanoprocessor continued to be made into the late 1980’s and many of them are still in use today running various HP equipment.

Nanoprocessor User Manual – October 1974

A big thank you to Larry Bower, the project lead and designer of the Nanoprocessor, who donated several prototypes, a complete mask set, and very early documentation on the Nanoprocessor (amongst some other goodies)

Documentation so ealy it has many hand written parts, and some corrections.  This had to be a very annoying oops if it wasn’t caught early on.  Even Engineers get their left and right mixed up on occasion

 

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CPU of the Day

July 8th, 2020 ~ by admin

News: New Server for CPU Shack

It took way longer then it should have but over the last 5 weeks CPUShack.com was transitioned to a new server.  We were hosted on a Media Temple GRID server, which got less and less suited for WordPress over the years so ended up with hundred of dollars in overages everytime i posted an article.  CPU Shack is now on a virtual dedicated server which should be faster and more flexible.  Next step will be to add SSL support, to keep up with current web guidelines.

If you notice anything not working, be sure to let me know.

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Museum News

June 14th, 2020 ~ by admin

AMD Am29C327: How to Take a Picture of a Black Hole

AMD AM29C327 Engineering Sample -1990

Recently I came across one of the more unusual members of the AMD Am29300 series.  These were a set of processor elements (multipliers, FPUs, ALUS, registers) AMD designed to support AM29000 CPUs as well as for the bases for custom CPU designs.  Some. like the AM29C323 multiplier found common use in video game and other applications.  Others like the AM29C325 32-bit FPU were used in educational experiments and research.  The 29300 (Bipolar) and 29C300 (CMOS) series are not particularly well known due to their obscure and often deeply specialized used.  At the top of the series lies the AMD AM29C327 Double precision (64-bit) FPU.  This FPU has a few tricks up its sleeves and is about as obscure in use as it gets….

The Am29C327 was on of the first chips made on AMDs CS-11A 1.2u processor (an enhancement of the 1.6u CS-11) .  It was first announced in 1987 with sampling to begin in late 1988.  The ‘327 contained over 250,000 transistors and was packed in a 169PGA package.  It is a IEEE754 compliant double precision FPU but also supports IBM and DEC formats.  It has 3 32-bit buses (2 for input and one for output) that, when multiplexed, allow for 64-bit maths.  Its little brother, the ‘325, only supports 32-bit math, and comes in a 145PGA package with around 30,000 transistors (11,000 gates).  So why does going to double precision involve nearly 10 times the transistor count?  It turns out that the ‘327 is more closely related to an actual CPU then a normal FPU.  The ‘325 has all of 8 instructions (add/sub, mult const subtraction and some conversions), while the ‘327 supports 58 instructions.  Of those 58 instructions 35 are Floating point, 1 is system management, and the other 22? Those are a full set of integer instructions.  The ‘327 actually supports more then just floating point.  Its internal ALU is a 64-bit 3 input design, allowing inputs from either the 2 external inputs, the output, a set of 8 64-bit registers, or a set of 6 constants.  Its instructions are 14 bits and it supports pipelining for even faster calculations.  Interestingly, pipelining can be disabled and the FPU will work in straight flow through mode.  So where is such a complicated chip used? Doing complicated math of course.

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May 13th, 2020 ~ by admin

Chapter 2: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997

At the end of 2018, I started one project, which was called “Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997”. It was dedicated to the ALR Revolution 6×6 super server with six Intel Pentium Pro processors and a cost comparable to that of a brand new Ferrari in 1997. It took some 450 days and finally follows the continuation of the story, the super server received the long-awaited upgrade – six Intel Pentium II Overdrive 333 MHz Processors! For those years, such power was simply colossal, but how it compares with today’s and how much increased performance you will learn from this article.

I’ll admit 450 days is quite a long time, so I will briefly recall the contents of the previous series of the article.
And it all started like this: plunging into the world of mainframes and supercomputers , I wanted to try some super powerful system and the choice fell on the ALR Revolution 6×6 super server, which had six Socket 8 and supported up to 4 GB of RAM. For the late 90s, these were scary numbers, as well as its cost. One processor for such a system was estimated by Intel at $ 2675, and six were required, for one module of 256 MB of server memory it was necessary to pay $ 3500, and sixteen sticks were needed to get the coveted 4 GB of RAM.

A disk subsystem was also available with seven raid controllers and an 860 GB disk array, a twenty-kilogram power supply unit and the server itself … As a result, it was possible to reach amounts from 270 to 500 thousand dollars, and if you add here the inflation level over the years, these numbers will range from 435 to almost 800 thousand dollars. Now, in terms of performance, any low-cost computer will be faster than this monster, but the very fact of having such an opportunity in 2020, to feel the full power of that time, makes these large numbers insignificant, it is much more important to find and assemble such a monster.

ALR 6×6 Available Options

In the previous story, I studied performance with six Intel Pentium Pro processors with a frequency of 200 MHz and a 256 KB second-level cache and even overclocked all six copies to 240 MHz. As well as six top-end Intel Pentium Pro “black color” with a frequency of 200 MHz and a 1M L2 cache, which were able to overclock to 233 MHz. In my configuration, I had 2 GB of RAM standard FPM, 16 memory modules of 128 MB, which took over 4 minutes to initialize during the initial POST procedure.

Four gigabytes of RAM would bring this figure to 9 minutes, which is comparable to accelerating a train or taking off an airplane, although the latter can do it much faster. But then, having loaded at my disposal, six physical cores arrived at once, but without the support of MMX and especially SSE instructions.

Intel Pentium II Overdrive 333 MHz processor

The basis of any computer is the central processor. Intel Pentium Pro processors first appeared in 1995. Then there were the usual Pentiums without the Pro prefix, but this prefix in the name of the models said that these processors are positioned primarily as solutions for servers and workstations with their special Socket 8. The usual Intel Pentiums were installed in Socket 5 and 7. A significant difference between the Pro and the regular version of the Pentium desktop was the presence of a second-level cache in the Pro version, which, being on the same package, worked at the processor’s core frequency, thus allowing it to significantly increase performance.

For the various Intel Pentium Pro models, the L2 cache size ranged from 256 KB to 1 MB. Pentium Pro’s first level cache was 16 KB, of which 8 KB was for data and the same for instructions. For the subsequent Intel Pentium-IIs, the second-level cache worked at half the processor core frequency and amounted to 512 KB for all models, and it was located in the form of separate microcircuits on the cartridge at a distance from the CPU die itself. The L1 cache size was doubled in size to 32K, which offset the performance hit of the slower L2 cache.

Pentium Pro Slot 1 Slockets – Also made were Slot 2 versions.

The tested processors were produced at a 350 nm process technology. The number of transistors in the Pentium Pro totaled 5.5 million for the processor core itself and as many as 15.5 – 31 million were in the L2 cache memory, depending on its size. The L2 cache itself was located on a separate die near the CPU core. The processor had a free multiplier and the system bus frequency, depending on the model, was 60 or 66 MHz. Overclocking of the processor rested on overclocking the L2 cache, it the limiting factor.

CPU core on the right, L2 cache on the left

The Intel Pentium II Overdrive 333 MHz was a very interesting processor. This processor appeared, it can be said, thanks to the US Government, which funded a program to create supercomputers for modeling nuclear explosions and tracking the state of the country’s nuclear arsenal. The US government allocated funds for the construction of such a supercomputer, Intel won the tender and in 1997 handed over a turnkey supercomputer called “ASCI Red”.

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April 16th, 2020 ~ by admin

DEC M7260 KD11-A CPU: The PDP-11 Goes MSI

PDP-11/05 Front Panel (pic from vintage_electron)

Back in 1972 DEC released the ‘budget’ PDP-11/05 16-bit computer.  The original PDP-11/20 had been released 3 years before and its CPU (the KA11) was based on simple TTL, its ALU could perform adds and that was all, which meant its designers had to get creative in implementing the instruction set.  By 1972 however things had changed, there still was no 16-bit processors available but there was now single chip 4-bit ALU’s.  The ALU was the famous 74181 and formed the heart of the KD11-A, DEC’s 4th processor design (the ‘third’ was the KB11-A which was similar but based on the faster 74S181 and used in the PDP-11/45 and released at the same time) .

The KD11-A consisted of a pair of boards, the M7260 Data Path Module and the M7261 Control Logic and Microprogram Module.  All the processor functional components are contained on these modules. The M7260 Data Path Module contains: data path logic, processor status word logic, auxiliary arithmetic logic unit control, instruction register and decoding logic, and serial communications line interface. The M7261 Control Logic and Microprogram Module contains: internal address detecting logic, stack control logic, Unibus control logic, priority arbitration logic, Unibus drivers and receivers, microbranch logic, microprogram counter, control store logic, power fail logic, line clock, and processor clock.   The M7260 was he brain, and the M7261 told it what to do, containing the microcode to implement the PDP-11 instruction set.  This was the first version (with the 11/45) of the PDP-11 that was microcoded.

Fairchild 934159 74181 MSI 4-bit ALU made on a Bipolar – This example from very early 1971

The KD11-A ran off a single 150ns clock resulting in a raw clock speed of 6.67MHz, however performance was limited by memory access speed. The PDP-11/05 supported up to 32K Words (64KB) of core memory and this memory could only run at a 980ns cycle time.  This limited the 11/05 performance to around 1MHz.  This was still quite good for 1972!.

The 74181 was capable of running at 42MHz (and 90MHz for the 74S181 Schottky TTL versions) but in a set of 4 this drops to about 27MHz (with the carry generator taking some time).   Speed, however, is usually limited by other things rather then the ALU itself.   The 74181 ALU contains the equivalent of 62 logic gates (170 transistors) and can perform 16 different arithmetic and logic functions on a pair of 4-bit inputs.  Ken Shirriff did an excellent die level analysis of a ‘181 thats worth reading.  It includes pretty pictures even.

DEC M7260 – Data Path for the KD11-B CPU – Dated July 1972

This particular KD11-A board is one of the very first made.  It is dated July 20th 1972, a month after the initial release of the 11/05.  The big white chip is a General Instruments AY-5-1012 UART.  To its right you can see thr 4 74181 ALUs.  Each is 4-bit and together they form a complete 16-bit ALU for the CPU. A 74150 Multiplexer helps determine what data goes where.  The 74182 is the Look ahead carry generator for the ‘181’s.  Most of the rest of the chips on the board are ROMs and supporting logic.  There is also 4 Intel C3101A 35ns SRAM chips, these are 16×4 SRAMs used as scratch pad memories and only were used in the very first version of the CPU (later versions replaced them with cheaper 7489 TTL versions).  The Scratch Pad Memory is what forms the registers for the CPU.  There are 16 16-bit registers with the the first 6, R0-R5 being general purpose registers and the rest special purpose such as the Program Counter, Interrupt Vector, etc.

M7261 Control module – Contains the microcode for the CPU (pic from xlat.livejournal.com)

Another interesting point on this board is the very large amount of green wires running on the board.  These are called ECO wires, which are ‘Engineering Change Order’ wires, and are placed, by hand, after the board is made to correct faults in the board layout.  The goal is to not have these as they are expensive and delicate and can result in failures down the road, so further revisions of the board would have these fixed/implemented in the PCB.  You do not see these much at all any more as modern design/testing tools virtually eliminate the possibility of a faulty PCB layout making it into production.

When it was released the ~1MHz 11/05 cost $25,000, which in 2020 US Dollars is around $154,000.  THe PDP-11 series ended up being one of the most popular minicomputers, selling over 600,000 units over the years.  Later versions like the LSI-11 series moved the entire CPU to a single LSI chip, adding Extended Instructions, Floating Point Instructions, faster memories and other performance enhancements well into the 1980’s.   It was also widely comied, and enhanced in the Soviet Union and Russia.  It was on a Soviet PDP-11 clone that Tetris was developed, a game we are all rather familiar with.

Its amazing to see where computers have come in the span of but a few decades. but these important parts of history continue to be used.  Perhaps not the 11/05, but there are many PDP-11 systems still working away, typically inindustrial environments, ironically helping produce things likely far more advanced then themselves.

March 20th, 2020 ~ by admin

The Intel N60066: Unwrapping a Mystery

Fischer & Porter 53MC5 – The beginning of the Mystery

One day last summer, I was browsing the deep dark corners for processors, a fun, yet dangerous activity.  I happened upon a lot of PCBs from some older industrial automation equipment.  No real information was provided (those buying these boards clearly would already know what they needed).  They did however have a RTC, an EPROM a 16MHz crystal, and a large 84-pin PLCC.  That PLCC was marked as an Intel N60066.  Seeing such a large chip, surrounded by such components almost always means its some sort of processor or microcontroller.  The problem is, there is no known Intel 60066 part.  The chips were all made in the late 80’s and early 90’s and had  1980 and 1985 copyrights.  A 1980 copyright typically screams MCS-51, as that was when it was introduced and nearly all such chips bear an Intel 1980 mark.

Intel N60066

The boards themselves were dated from 1990 all the way to the early 2000’s (I bought a lot of them, another problem I have).  Some had the part number 53MC5 and the logo of Fischer & Porter.  Fischer & Porter has existed since the 1930’s and was a leader in instrumentation.  They were bought by Elsag Bailey Process Automation (EBPA) in 1994 which itself was swallowed up by ABB in 1999.  The boards design was largely unchanged through all of these transitions. Searching for documentation on the 53MC5 part number (its a Loop Controller) didn’t yield details on what the N60066 was unfortunately.  The only thing left to do was to set it on fire…

Unfortunately this is the only way I currently have for opening plastic IC’s (I need to get some DMSO to try apparently).  After some careful work with the torch and some rough cleaning of the resulting die it was readily apparent that this was an MCU of some sort.  The die itself was marked… 1989 60066.  This wasn’t a custom marked standard product, this was a custom product by Intel for this application, a very surprising thing indeed.  Unlike other companies such as Motorola, Intel was not well known for custom designs/ASICs.  This wasn’t their market or business plan.  Intel made products to suit the needs they saw, if that worked for the end user, great, if not, perhaps you could look elsewhere.  They would gladly modify specs/testing of EXISTING parts, such as wider voltage ranges, or different timings, but a complete custom product? Nope, go talk to an ASIC design house.  Its likely Fischer & Porter ordered enough of these to make it worth Intel’s effort.

Knowing this was an MCU and suspecting a MCS-51 further searching revealed the answer, and it came from the most unusual of places.  In 2009 the US NRC (Nuclear Regulatory Commission) determined there was no adequate Probabilistic Risk Assessment (PRA) for Digital systems in their agency, so set about determining how best to calculate risk of digitally controlled systems.  They analyzed a system used to control feedwater in nuclear reactors.  These are critical systems responsible for making sure the reactor is kept with the right amount of cooling water at the right time, failure of course is not an option.  The 53MC5 is what is used for controlling the valves.  In this document we find this nugget:

The controller is an 8051 processor on board an application-specific integrated circuit (ASIC) chip that performs a variety of functions.

Well that certainly helps, it is indeed a custom ASIC based on an 8051.  The report also provided a diagram showing the ASIC system.  This is an 8051 core with RAM/ROM (normal) as well as a Watchdog timer, a PAL, I/O Buffers, and Address Logic.

I sent a couple of these chips to my friend Antoine in France for a proper die shot, which he is quite amazing at.

Intel N60066 die – 8051 core on the left. Die shot by Antoine Bercovici

The 8051 core is on the left of the die, with its RAM/ROM.  A very large PLA occupies the bottom right side of the day.  In the upper right is presumably the external watchdog timer for the ASIC.  The lines crossing the die mostly vertically are a top metal layer used for connecting all the various sections.

The hunt for a new CPU/MCU is part of the thrill of collecting.  The satisfaction of finding out what a mystery chip is can be worth many hours of dead ends in researching it.  Its not common to have to go to the NRC to find the answer though.

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CPU of the Day

February 9th, 2020 ~ by admin

ESA Solar Orbiter: When SPARCs Fly

ESA ERC-32SC

ERC-32SC – SPARC V7 MCM with RAM and MIL-STD-1553

In a few hours (assuming no more delays, UPDATE: Launch Successful) the joint NASA/ESA Solar Orbiter mission will launch on a ULA Atlas 5 Rocket out of Florida, USA.  This is a mission a long time coming for the ESA, which like NASA has to get its funding from the government, except in the case of ESA, that involves the governments of many countries in the EU, which can make planning a bit more tricky.  The mission was originally baselined in 2011 and hoped to launch in…2013…then 2017..then 2018 and finally a launch date in 2020.  The original proposal dates to the late 1990’s as a mission to replace the joint NASA/ESA SOHO Solar mission that had launched in 1995.  This creates some interesting design choices for a mission, as designing often happens before a mission is completely approved/funded.  For Solar Orbiter this is one of the main reasons for it being powered by a computer that by today’s standards is rather dated, space standards no less!

Solar Orbiter – ESA

The Solar Orbiter is powered by a processor designed by the ESA, the ERC-32SC.  This is the first generation of processors designed by the ESA.  It is a SPARC V7 compliant processor running at 25MHz and capable of 20MIPS.  The ERC-32SC is a single chip version of the original ERC-32 which was a MCM (Multi chip Module) containing 3 dies that made up the processor (the Atmel/Temic TSC691 Integer Unit TSC692 FPU and TSC693 Memory Controller) that was made on a 0.8u CMOS process.  The Single chip version was made possible by a processes shrink to 0.5u.  It was also made by Atmel,  (whom acquired Temic) and is commercially known as the TSC695 as it is designed for space use, is capable of handling a 300krad Total Ionizing Dose of radiation.  The computer used in the Solar Orbiter was built by RUAG and has two seperate ERC-32SC processor systems for redundancy.  Each of the ERC-32SCs are actually mounted on a MCM, the single chip SPARC, 48MB of DRAM (38 of which is used, the remainder is for Error Detection/Correction via Reed Solomon method), and a MIL-STD-1553 bus controller/RTC/IO are included in the package.

Fujitsu MB86900 – Original SPARC V7 Processor from 1987

The original specifications for this processor were developed back in the 1990’s, which is why it is a SPARC V7, equivalent to the very first Sun SPARC workstations of the late 1980’s powered by the likes of the Fujitsu MB86900/MB86901.  The ESA has developed several follow on processors since, all based on the later SPARC V8 architecture.  They are faster, and more efficient then the ERC-32SC, with some even being dual core processors.  They are known as the LEON-2 and the later LEON-3.  LEON2 has a 5-stage pipeline and no SMP support, while LEON3 increases the pipeline to 7-stages and adds SMP support.  LEON3 is also a VHDL core able to be added to many ASICS/FPGAs (LEON2 is a hard core).  The Solar Orbiter also has both LEON2 and LEON3 processors on board as well…

The Solar Orbiter caries with is 10 different scientific instruments, and each of them has their own processing subsystem, 9 of which are powered by LEON SPARC processors.  Its common for the main processor of a spacecraft to be the most powerful, but in this case the instruments each possess their own processor more powerful then that of the main spacecraft computer.   This is in large part due to many of these instruments being designed well after the original spacecraft bus and systems were baselined.  Payloads can be added/changed much later in the design of the spacecraft allowing their designers to use more modern computers.

Instrument Processor(s) Notes
Solar Orbiter OBC ERC-32SC – Atmel TSC695 Spacecraft Platform Processor
SoloHi LEON3FT – Microsemi RTAX2000 FPGA
MAG-IBS/OBS LEON3FT – Microsemi RTAX2000 FPGA
RPW-SCM/ANT LEON3FT – Microsemi RTAX4000D FPGA
LEON3FT – Cobham UT699
Two processors
SWA-HIS/EAS/PAS LEON2FT – Atmel AT697F up to 100MHz
EPD-SIS LEON2FT – IP Core
STIX LEON3FT – Microsemi RTAX2000 FPGA
EUI LEON3FT – Cobham UT699 66MHz Single core
METIS LEON2FT – Atmel AT697F
PHI LEON3FT – Cobham GR712RC Dual core up to 100MHz
SPICE 8051 + FPGA Long live the MCS-51

There is also likely more processors on this mission as well, but it can be hard to track them all down, nearly every system has its own processing (star trackers, radios/ attitude control etc)

So as you watch the launch tonight, and perhaps see science/pictures from the Solar Orbiter (or just benefit from its added help in predicting solar storms and allowing us here on Earth to prepare for them better) think of all the SPARCs it has taken to make it function.

 

January 24th, 2020 ~ by admin

ARMing the Modems of the 1990’s

Racks of external modems at an ISP back in the day

Back in the 1990’s I worked at several ISP’s in my hometown.  These were the days of dial up, and by working at the ISP I got free dial up access which my family and I enjoyed.  We had several racks (white wire racks) of external modems for dial in.  This was the most common solution for smaller ISPs.  External modems were usually more reliable, cheap and easy to replace if/when they failed (and they did).  They got warm so it wasn’t uncommon to see a fan running to help move more air.  Surprisingly I could only find a few pictures of a such installations but you get that idea.

By the late 1990’s as dial in access and ISPs grew to be major concerns dial up solutions became much more sophisticated.  Gone were wire racks of modems and in were rackmount all in one dial in solutions.  These included boards that hosted dozens of modems on one PCB. with their own processing and management built in.  One of the largest companies for these solutions was Ascend Communications.  Their ‘MAX TNT’ modem solution once boasted over 2 million dial up ports during the 1990’s.  Such was Ascends popularity that they merged with Lucent in 1999, a deal that was the biggest ever at its time, valued at over $24 Billion ($37 Billion in 2020 USD). It wasn’t just traditional ISPs that needed dial up access, ATM’s and Credit Card processing became huge users as well.  It wasn’t uncommon to try to run a credit card at a store in the 1990’s and have to wait, because the machine got a busy signal.  The pictured Ascend board has 48 modems on a single PCB, and would be in a rack or case with several more boards, supporting 100s of simultaneous connections.

Ascen CSM/3 – 16x Conexant RL56CSMV/3 Chips provide 48 modems on one board.

Ascend’s technology was based primarily on modem chips provided by Conexant (Rockwell Semiconductor before 1999).  Rockwell had a long history of making modem controllers, dating back to the 1970’s.  Most of their modem controllers up through the 80’s and early 90’s were based on a derivative of the 6502  processor.  This 8-bit CPU was more the adequate for personal use modems up to 33.6kbaud or so, but began to become inadequate for some of the higher end modems of the 1990’s.  These ran at 56k, supported various voice. fax, and data modes and handled a lot of their own DSP needs as well.  Rockwell’s solution was to move to an ARM based solution, and integrate everything on chip.

One of the results of this was the Anyport Multiservice Access Processor. It was called the Multiservice Access Process because it handled, voice, data, 33.6/56k, ISDN, cellular, FAX and several other types of data access, and it did so in triplicate.  The RL56CSMV/3 supported 3 different ports on one chip.  The CSM3 series was the very first ARM cored device Rockwell produced.  Rockwell had licensed the ARM810 (not very common), the ARM7TDMI and a ‘future ARM architecture’ (which was the ARM9) back in January of 1997.  In less then two

Conexant RL56CSM/3 R7177-24 ARM7 (non-V version has no voice support)

years Rockwell had designed and released the first AnyPort device, remarkable at the time.  The CSM/CSMV used the ARM7TDMI running at 40MHz and made on a 0.35u process.  The CSM/CSMV has another interesting feature, and thats the backside of the chip….

Take a look of the backside of the 35mm BGA chip, the ball arrangement is very unusual!  There is a ring of balls around the outer edge and 4 squares of 16 balls inside of that.  This is a multi-die BGA package.  There are 4 die inside one BGA package, three dies for the 3 Digital Data Pumps (DDPs) and a seperate die for the ARM7 MCU (which is made on a different process then the mixed signal DDPs).  Most of the balls in the 16×16 squares are to be connected to GND, and used for thermal dissipation (dissipating heat via the main PCBs ground plane).  Its not uncommon to see multidie packages today, but a multi die BGA package in 1999 was fairly innovative.

Surprisingly many of these chips are still in service, in today’s world of high speed broadband connections there are still many who are stuck on dial up.  As recently as 2015 AOL was still serving 2.1 million dial up customs in the US (out of around 10 million dial up customers total), which was still netting the company nearly half a billion dollars a year (by far their largest source of revenue at the time.  There is also still plenty of other infrastructure that still rely on dial up, ISDN, and even FAX services that require end point connections like the CSMV so its end is probably still a long ways off.