June 10th, 2018 ~ by admin

The Collector’s Guide to Vintage Intel Microchips

The CPU Shack Museum is proud to announce the availability of The Collector’s guide to Vintage Intel Microchips, written by George Phillips Jr. This e-book (PDF) contains over 1300 pages, and 900 photographs of Intel Microchips from the 1960’s and 70’s along with their functions, package variations, rarity, and valuations.  Everything from the 3101 Static RAM to the i4004 4-bit processor. The author, George Phillips, has moved this book into public domain.  Originally published back in 2007 it is still a very useful resource.  Being 10 years old, some of the values are inaccurate and there has been a few more Intel chip types from the 1970’s found since then, as well as some different package/marking variations.  However the Guide is really an important resource for any collection that includes Intel IC’s from the 1970’s.

I have been collecting information for an update to it for some time, so if you have any Intel chips/variations not in this guide, feel free to let me know.

You can download The Collector’s Guide to Vintage Intel Microchips here (pdf 22.9MB)

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Products, Research

May 27th, 2018 ~ by admin

Mainframes and Supercomputers, From the Beginning Till Today.

This article is provided by guest author max1024, hailing from Belarus.  I have provided some minor edits/tweaks in the translation from Belarusian to English.

Mainframes and Supercomputers, From the Beginning Till Today.

Introduction

We all have computers that we like to use, but there are also more productive options in the form of servers with two or even four processor sockets. And then one day I was interested, but what is even faster? And the answer to my question led me to a separate class of computers: super-computers and mainframes. How this class of computer equipment developed, as it was in the past and what it has achieved now, with what figures of performance it operated and whether it is possible to use such machines at home, I will try to explain all this in this article.

FLOPS’s

First you need to determine what the super-computer differs from the mainframe and which is faster. Supercomputers are called the fastest computers. Their main difference from mainframes is that all the computing resources of such a computer are aimed at solving one global problem in the shortest possible time. Mainframes on the contrary solve at once a lot of different tasks. Supercomputers are at the very top of any computer charts and as a result faster than mainframes.

The need for mankind to quickly solve various problems has always existed, but the impetus for the emergence of superfast machines was the arms race of well-known superpower countries and the need for nuclear calculations for the design and modeling of nuclear explosions and weapons. To create an atomic weapon, colossal computational power was required, since neither physicists nor mathematicians were able to calculate and make long-term forecasts using the colossal amounts of data by hand. For such purposes, a computer “brain” was required. Further, the military purposes smoothly passed into biological, chemical, astronomical, meteorological and others. All this made it necessary to invent not just a personal computer, but something more, so the first mainframes and supercomputers appeared.

The beginning of the production of ultrafast machines falls on the mid-1960s. An important criterion for any machine was its performance. And here on each user speaks of the well-known abbreviation “FLOPS”. Most of those who overclock or test processors for stability are likely to use the utility “LinX”, which gives the final result of performance in Gigaflops. “FLOPS” means FLoating-point Operations Per Second, is a non-system specific unit used to measure the performance of any computer and shows how many floating-point arithmetic operations per second the given computing system performs.

“LinX” is a benchmark of “Intel Linpack” with a convenient graphical environment and is designed to simplify performance checks and stability of the system using the Intel Linpack (Math Kernel Library) test. In turn, Linpack is the most popular software product for evaluating the performance of supercomputers and mainframes included in the TOP500 supercomputer ranking, which is made twice a year by specialists in the United States from the Lawrence Berkeley National Laboratory and the University of Tennessee.

When correlating the results in Giga, Mega and Terra-FLOPS, it should be remembered that the performance results of supercomputers always are based on 64-bit processing, while in everyday life the processors or graphics cards producers can indicate performance on 32-bit data, thereby the result may seem to be doubled.

The Beginning

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April 11th, 2018 ~ by admin

PowerPC Processor for TESS Planet Hunter – Updated

TESS Orbiter – Freescale (now NXP) 2010  PowerPC e500

UPDATE: I received a note from a NASA engineer that the final flight DHU was made by SEAKR Engineering rather then Space Micro.  It turns out MIT pursued 2 different DHU systems in the design of TESS.  The Space Micro IPC 7000 was referred to as the DHU and a system by SEAKR (the Athena-3) was selected as the ADHU (Alternate Data Handling Unit).  Apparently MIT wasn’t sure which would be best so essentially characterized both (and most documentation from early on shows the Space Micro system).  In the end however, the SEAKR Athena-3 Single Board computer was selected.

If all goes well, in a few days the NASA TESS (Transiting Exoplanet Survey Satellite) will be launched on a SpaceX Falcon 9 rocket to startits mission to survey a large portion of the sky for possibly Earth-like planets.  TESS’s finds will make great candidates for further study by either Hubble, or JWST (when it finally launches).  While TESS can see transiting planets (the dimming of a star as an exoplanet passes in front of it) it cannot determine much about its composition, or the composition of its atmosphere.  However, having a list of exoplanets to further check out, especially Earth-sized ones, it’s a big help.  TESS was created as part of the NASA Medium Class Explorers Program (MIDEX) which is for mission up to around $200 Million total cost to NASA (not including launch).  TESS itself cost about $75 million (developed in large part by MIT and built by Orbital-ATK on their LEOStar-2 Platform) and the launch services contract was $87 Million with the remainder taken by operations and contingency funding.

Space Micro Proton 400k with Freescale 2020 processor

That makes this one of the least expensive NASA missions, but one that has engendered much more public interest then its cost suggests.  Finding alien worlds captivates people hearts and minds.  So what is at the heart of the TESS orbiter?  Obviously the premier technology is its 4 cameras that will scan the sky, but the computer that powers these is no less interesting.

The 4 cameras are interfaced to a Data Handling Unit (DHU).  Initially the DHU was to be the Space Micro IPC-7000 computer.  The IPC-7000 consists of a TI TMS320C67xx 32-bit DSP and a pair of Xilinx Virtex-7 FPGAS.  They handle all the pre-processing of the imagery collected by the cameras, making it into a format that is easily transmitted back to earth.  The rest of the spacecraft functions (such as actually sending/storing the data and other space craft house-keeping) is handled by a Space Micro Proton 400k SBC.  The Proton 400k is based on a Freescale 2020 1GHz Dual Core PowerPC processor made on a 0.45u process..  Each PowerPC e500v2 core has a 7-stage pipeline with 32K of I-cache and 32K of D-Cache and shares a single 512K L2 Cache.  The computer also containing a pair of 192GB solid state memory boards for buffering imagery data (data is relayed to Earth only once per orbit, so it needs to store data from around 14 days).

Athena-3 SBC – Powered by a 1.067GHz Freescale P2010 Processor

The final flight version of TESS switched to an ADHU made by SEAKR Engineering.  This uses a very similar setup but a bit less powerful processor.  The heart of the ADHU is the Freescale P2010 e500 processor at 1066MHz with 1GB of DDR2 RAM and 1-4GB of Flash.  This is the single core version of the P2020 used in the initial Proton 400k.  The ADHU also includes a RCC5 triple Xilinx Virtex-5 FPGA board to handle additional camera processing functions (and anything else not handled by the P2010 processor).  Solid state storage is a Gen 3 FMC also by SEAKR, containing 3 boards with a total of 192GB of Flash.  The ADHU handled all of the science, processing the raw camera data into useful science data and handling the sending of data to the 100-125MBit/sec Ka-band transmitter.  It also supplies some star reference information used by the MAU (Master Avionics Unit) computer to provide finer attitude control of the satellite.  The MAU is the LeoStar-2 Satellites main computer, and handles all the mechanics of flying the spacecraft outside of the science work done by the ADHU.

Freescale P2020 Processor

In many ways this is a very advanced processor compared to the RAD750 processors we often see on large scale NASA missions.  The Freescale 2020/2010 is not an inherently radiation hardened design, however both Space Micro and SEAKR  implements many radiation mitigating designs in the system design to compensate for this.  It is not as robust as the RAD750 but it is a $75 million earth satellite with a target mission life of 2-years so it doesn’t need to be. The 2020 processor does give TESS tremendous processing power for a scientific satellite, allowing for a lot of pre-processing of the imagery.  This allows TESS to handle much of the grunt work, and send scientists here on Earth only the very best data, in a format that is the most useful to them.

 

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CPU of the Day

March 24th, 2018 ~ by admin

Making MultiCore: A Slice of Sandy

Intel Sandy Bridge-EP 8-core dies with 6 cores enabled. Note the TOP and BOTTOM markings (click image for large version)

Recently a pair of interesting Intel Engineering Samples came to The CPU Shack.  They are in a LGA2011 package and dated week 33 of 2010.  The part number is CM8062103008562 which makes them some rather early Sandy Bridge-EP samples.  The original Sandy Bridge was demo’d in 2009 and released in early 2011.  So Intel was making the next version, even before the original made it to market.  The ‘EP’ was finally released in late 2011, over a year after these samples were made.  Sandy Bridge-EP brought some enhancements to the architecture, including support for 8-core processors (doubling the original 4).  The layout was also rather different, with the cores and peripherals laid out such that a bi-direction communications ring could handle all inter-chip communication.

Sandy Bridge-EP 8-core die layout. Note the ring around the inside that provides communications between the peripherals on the top and bottom, and the 8-cores. (image originally from pc.watch.impress.co.jp)

Sandy Bridge EP supports 2, 4, 6 and 8 cores but Intel only produced two die versions, one with 4 cores, and one with 8 cores.  A die with 4 cores could be made to work as a dual core or quad, and an 8-core die could conceivably be used to handle any of the core counts.  This greatly simplifies manufacturing.  The less physical versions of a wafer you are making, the better optimized the process can be made.  If a bug or errata is found only 2 mask-sets need updated, rather then one for every core count/cache combination.  This however presents an interesting question..What happens when you disable cores?

That is the purpose of the above samples, testing the effects of disabling a pair of cores on an 8-core die.  Both of the samples are a 6-core processor, but with 2 different cores disabled in each.  One has the ‘TOP’ six cores active, and the other the ‘BOTTOM’ six cores are active.  This may seem redundant but here the physical position of the cores really matters.  With 2 cores disabled this changes the timing in the ring bus around the die, and this may effect performance, so had to be tested.  Timing may have been changed slightly to account for the differences, and it may have been found that disabling 2 on the bottom resulted in different timings then disabling the 2 on the top.

Ideally Intel wants to have the ability to disable ANY combination of cores/cache on the die.  If a core or cache segment is defective, it should not result in the entire die being wasted, so a lot of testing was done to determine how to make the design as adaptable as possible.  Its rare we get to see a part from this testng, but we all get to enjoy its results.

March 21st, 2018 ~ by admin

Intel’s Chipped Chips

Early Intel 8080A processor (no date code) chipped and used in a Uni kit

Typically when collecting something, be it coins, cars or CPU’s having the most pristine unblemished example is highly desirable.  However, sometimes, the best example is one that isn’t perfect, in coin collecting it may be a rare double struck coin, or some other flaw that actually makes the coin more valuable.

In the 1970’s Intel put together many development kits for it’s processors.  These were to help engineers, companies, and even students learn how to use Intel’s products. Intel made several kits specifically for University use, including one based around the MCS-80 processor and another around the MCS-48 microcomputer.  The 8080 University kit came with an 8080 processor, and a variety of support chips, including RAM, EPROMs (usually 1702s), clock drivers, bus drivers etc.  They were often a mix of packages, including plastic, and ceramic, with many chips being marked ‘CS‘ which is Intel’s designation for a Customer Sample.

Military MC8080A CS from a Uni kit. Multiple chipped corners. Such damage often was a result of improper packing in an IC shipping tube.

The price of the kits was kept low, the purpose was to get people use to using Intel products, not to make money.  Due to this, Intel tried to build the kits in the most efficient way possible.  Almost every 8080 University kit included a working, but cosmetically damaged C8080A processor.  These were typically the white/gold ceramic variety with a chipped corner.   It was very common to see a MC8080A or MC8080A/B military spec processor in a University kit, the processor would function fine, but had  some damage, enough that it could not be sold as a mil-spec processor (which has requirements for screening out such damage). The damaged chip would simply be tested, stamped ‘CS‘ and stuck in a kit, ths saving Intel money and keeping a working processor from being wasted.   The same thing happened with the MCS-48 University kits, these included chips such as the D8035 or C8748 MCU, and again, often shipped with damaged chips.

It turns out that the most correct, authentic chip, in a University Kit, was the cosmetically challenged, and in a way, this makes them more uncommon and more interesting.  Its due to their damage that they were selected for the special use in a University kit.  The irony is that many times it was the highest end military screened chips, that ended up getting used in one of the lowest end products.

March 15th, 2018 ~ by admin

CPU of the Day: Intel Jayhawk – The Bird that Never Was

Intel Jayhawk Thermal Sample – 80548KZ000000 QBGC TV ES – Made in April 2004 Just 3 weeks before it was canceled

Perhaps fittingly the Jayhawk is not a bird, but rather a term used for guerilla fighters in Kansas during the American Civil War.   It is also the name of a small town in California 150 miles Northeast of Intel’s headquarters in Santa Clara.  It was also the chosen code name for a Processor Intel was working on back in 2003.  In 2003 Intel was working on the Pentium 4 Prescott processor, to be released in 2004 and its Xeon sibling, the Nocona (and related Irwindale),  The Prescott was a 31 stage design made on a 90nm process.  There was hopes it would hit 4+ GHz but in production it never did, though overclockers, with the help of LN2 cooling were able to achieve around 8GHz.  Increasing the length of the pipeline helps allow higher clock speeds, the Northwood core had a 20-stage pipeline so the Prescott was a rather big change.  There is a cost of lengthening the pipe, processors don’t always execute instructions in order, often guessing what will come next to speed up execution.  This is called speculative execution, processors also guess what data is to be needed next, and stick it in cache.  If either of these ‘guesses’ is wrong, the processor needs to flush the pipeline and start over, at a comparatively massive hit in performance.  This is what performance doesn’t always scale very linearly with clock speed.

Intel figured that this wouldn’t be an issue and so the Prescotts successor was to have a 40-50 stage pipeline.   THe hopes were for 5GHz at 90nm and 10GHz at 65nm. The desktop version was known as Tejas, and the server version, Jayhawk.  Initially these were to be made on the 90nm process, same as Prescott, before being transitioned to a 65nm process.  It increased the L1 cache to 24k (some sources say 32k) from the Prescotts 16k.  The Instruction trace cache was still 16k micro-ops, though this could have been increased.  L2 cache would have been 1MB at introduction and 2MB once the processor moved to a 65nm process.  Eight new instructions were to be added called ‘Tejas New Instructions’ or TNI, these later would become part of the SSSE3 instructions released with the Core 2 processor.  It also would bring ‘Azalia’ Intel’s High definition audio codec, DDR2 support, a 1066MHz bus, and PCI-Express support.  It turns out there was a problem….

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January 28th, 2018 ~ by admin

CPU of the Day: Tandem CLX 800 – It Takes 2 To Tango

TANDEM CLX 800 Processor – VLSI CMOS 1u process – 16MHz.

Tandem Computers was established way back in 1974, and was one of the first (if not the first) dedicated fault-tolerant computing companies.  They designed completely custom computers designed for use in high reliability transaction processing environments.  These were used for support of stock exchanges, banks, ATM networks, telephone/communications interchanges, and other areas where a computer failure would result in significant, costly, disruptions to business services.  Tandem was started by James Treybig, formally of HP, and a team he lured away from HP’s 3000 computer line.

Tandem computers are designed to do two things well, fail-over quickly when a failed part is detected.  This means that if a faulty processor or memory element is found, it can be automatically disabled, and processing continues, uninterrupted, on the rest of the system.  The other design element that Tandem perfected was allowing the computer to find and isolate intermittent problems.  If a processor or storage element ceases to work, that is relatively easy to figure out, but if a processor is glitchy, causing errors only occasionally, that can be much harder to find and can result in serious problems for the user.  This is known as ‘Fast Fail’ and today is a pretty standard concept, find the error, catch it, and prevent erroneous data from ever making it back into the database.  Tandem computers were designed from the ground up to be fault tolerant, disks were mirrors, power supplies, busses,

Tandem CLX 600 PCB (click for larger)

processors,all were redundant, but unlike some other systems, components were not kept as ‘hot spares’ sitting idle until something failed.  This kept hardware from being ‘wasted.’ Under normal operation if it was in the system, it was contributing to system performance.  A failed component then would reduce system performance until it was replaced/fixed, but a customer would not be paying for hardware that served them no purpose unless something broke.

To support these goals Tandem designed their own processors and instruction set architecture know as TNS (Tandem NonStop).  The first processors were a 16-bit design call the T/16 (later branded NonStop I) made out of TTL and SRAM chips spanning 2 PCBs.  Performance was around 0.7MIPS in 1976.  They were a stack based design similar to the HP3000 with added registers as well.  T/16 systems supported 2-16 processors. NonStop II, released in 1981, was similar, but supported the occasional 32-bit addressing, increasing accessible memory form 1 to 2MB per CPU and performance to 0.8MIPS.

The 1983 introduction of TXP saw a great performance improvement, up to 2.0 MIPS, but kept the same form factor.  The processor was implemented in TTL, with the addition of many PALs and added much better support for 32-bit addressing.  In 1986 the NonStop VLX was released, which moved to an ECL based processor.  This was a full 32-bit design, running at 12MHz (3MIPS) but still using discrete components and a new bus system as well.  This was to be the high end of the NonStop line, it was fast reliable, and rather large.  The desire for a more economical system to fit the needs of smaller customers led to a first for Tandem…

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December 19th, 2017 ~ by admin

Chip of the Day: TRW MPY-16AJ – Making Multiplication Manageable

TRW MPY16AJ – 1978

In Primary School students are tasked with memorizing their multiplication tables.  Taking the time to manually calculate 6×5 is much slower than simply committing the result to memory.  This allows more complex math to be processed quicker as the students skills develop.  Typically this is limited to numbers up to 12×12, resulting in 144 results to ‘store.’  In computing the same can be done.  A ROM can be used as a lookup table for multiplication.  The problem is it does not scale well.  Handling 4×4-bit multiplication requires a 256×8 ROM (2m+n addresses and m+n outputs). This could be handled by a many ROMs available in the 1970’s.  Anything more than 4-bits though was simply not possible.  This gave rise to the need for multipliers to calculate the result.

TRW MPY16AJ – Large Heatsink affixed to package to dissipate its 5W

This was a problem TRW set out to rectify in 1976.  TRW LSI Products was formed in the 1960’s to commercialize the transistor products that had been developed by Pacific Semiconductors, a division of TRW.  It was James Buie who invented the TTL logic gate in 1961 while working for TRW.  TTL went on to become the logic standard throughout the 1970’s and 80’s.   TRW was involved in aerospace, helping design planes, satellites, and missiles, fields that required processing of signals data, what became known as Digital Signal Processing (DSP).  In the 1980’s processors were designed to handle this, such as the TI TMS320 series, but in the 1970’s it had to be done with discrete components.  DSP systems had several needed blocks, Fast ADCs, ALUs, and multipliers.  TRW invented fast ADCs to handle the inputs, and ALUs were available such as AMDs Am2901 or even the TTL series 74181s.  Multipliers however were not widely available, especially for large bit-widths.

MPY-16 die

TRW’s first multiplier was a custom device to work with their own avionics processing system.  It was made on a Bipolar process, and multiplexed the entire product, using around 40 pins total (the entire product was multiplexed with the operands).  It could handle a multiply in 330ns worst case.  Interestingly yields of the device were considered ‘excellent’ at 3 working devices per wafer (out of 19 per wafer (most likely a 2″ wafer)).  Today, yields like that would be completely unacceptable.

TRW designed the MPY-16AJ as a brute-force 16×16 multiplier.  It was designed on a Bipolar process with around 3600 gates.  It implements a series of AND gates and CARRY-SAVE-ADDERS to implement the multiplication.  There are faster methods, but they come at the cost of complexity and power draw.  As designed the the MPY-16AJ dissipates 5 Watts while handling a signed (2’s complement) multiplication in a worse case 230ns).  They MPY16 was packaged in a large 64-pin package to limit the # of pins that had to be multiplexed.  The lower 16-bits of the product are multiplexed with one of the operands.  This is acceptable as in many applications the upper 16-bits of the product are sufficient accuracy.  The 64-pin package allowed for not less multiplexing, but also a much larger surface for heat dissipation.  A heatsink was also affixed to the package as well.

Micron (Russia) 1802VR5 – MPY16HJ Clone made in 1992

Later versions of the MPY-16 added support for unsigned multiplication as well (the MPY16H) and became the standard for 16-bit multipliers.  Compatible multipliers were made by Analog Devices (ADSP1016, 40-50ns at 150mW) and LOGIC LMU16/216) in CMOS, by Weitek (WTL1516/A/B, 50-100ns at 0.9-1.8W) in NMOS, by Synertek (SY66016 100ns at 1.5W) in HMOS, by AMD (Am29516 38ns at 4W) in ECL, as well as many others.  These were implemented internally with different processes, and different multiplier algorithms but externally they all mimicked the standard TRW MPY16J and served as the basis of many signal processing and high end math computers.  As a testament to their usefulness, the MPY16 was also copied by the USSR as the 1802VR5.  The TRW MPY16 was last made in the mid-1980’s but its clones continued to be made into the 1990’s.  Today its functions can be handled by any DSP, CPU or even coded into a FPGA, but for a time, the MPY16 multiplied the efficiency of many processing systems.

December 7th, 2017 ~ by admin

CPU of the Day: Hitachi HD6801S0PJ – Automotive 6801

Hitachi HD6801S0PJ – 1982 Automotive Spec 6801

The original Motorola MC6801 was released in 1977, built on a 5.1u NMOS process with 35,000 transistors (some sources say 25,000, which may be the ‘active’ transistor sites).  One of the very first customers was General Motors, you can read more about that in last years article on the 6801.  Hitachi was the primary second source for Motorola, primarily to supply the Japanese market, but they also competed with Motorola in the US market as well.  Hitachi released their version of the 6801 in 1980, with full production commencing in 1981.  It was made on a 3-micron NMOS process and was available in both a 1MHz speed (HD6801S0) and 1.25MHz (HD6801S5).  Around this time (1982) Hitachi was also transitioning their part numbering system.  Originally these parts were HD468xx… which was a bit confusing so they dropped the ‘4’.  For several years in the early 1980’s it is not uncommon to find parts with either, or both part numbers on them.

The pictured Hitachi HD6801S0P in interesting for a couple reasons.  The A00 denoted the ROM code for the 2K of onboard ROM.  A00 means that it is unprogrammed.  This would be useful for testing the 6801 with an external EPROM etc.  The ‘J’ on the package denotes that this device is a industrial/automotive spec part with an increased temperature range, in this case -40-85C.  Hitachi date codes are different from other manufacturers but are relatively simple.  The code 2E1 denotes the first week (1) of May (E) in 1982 (2).

Hitachi marked with both old and new part numbers
HD46800DP and HD6800P – dated 3F1 – First week of June 1983

Year* Month** Week
8 – 1978 A – January 1 – Week 1
9 – 1979 B – February 2 – Week 2
0 – 1980 C – March 3 – Week 3
1 – 1981 D – April 4 – Week 4
2 -1982 E – May 5 – Week 5
3 – 1983 F – June
4 – 1984 G – July
5 – 1985 H – August
6 – 1986 J – September
7 – 1987 K – October
8 – 1988 L – November
9 – 1989 M – December

*Years repeat, so 0 is used from 1980 and 1990
** ‘I’ is skipped to avoid confusion with the number ‘1’

What is perhaps more interesting is what came with this CPU when the museum got it.  Its often hard to figure out what a CPU/MCU was used in, or what it was for, its provenance.  This 6801 offers some help.  It came in an original Hitachi box, with a copy of a fax from Hitachi in Japan to the Hitachi sales office in the USA.  The fax denotes that these are qualification samples, automotive spec, and for a particular customer.  That customer is Chrysler (the automotive company now owned by Fiat).

Fax from Hitachi Japan stating use of the HD6801 samples

Also included on the fax is an original Japanese date stamp (June 1982 (Showa year 57)) .  These 6801s were fresh off the production line, having been made only a few weeks earlier.   The fax states these are for Chrysler in Huntsville, AL. with a reminder that they are “Not for Detroit” (where most of Chrysler production was.  That is an interesting addition, and important, as Chrysler did (it closed in 2011) have a very large presence in Huntsville, AL.  Huntsville is known as Rocket City, home of the Redstone Arsenal, where a large amount of US rocket, missile, and space engineering have taken place.  It was also the home of Chrysler Electronics (as well as most all of Chrysler’s military and space programs.  It was Chrysler who built the Saturn 1 and Saturn 1B upper stages for the NASA Apollo program.  Chrysler Electronics also built much of the Grown system electronics for the Apollo program as well as vehicle testing equipment for the M1 tank, the M2/3 Bradley and a host of other military programs.

Chrysler SERV – Space Shuttle Concept

Chrysler also proposed the Single-stage Earth-orbital Reusable Vehicle (SERV) during the design phase of what became the Shuttle program.

In the early 1970’s electronic use in cars was growing rapidly, leading Chrysler to greatly expand their presence in Huntsville.  These 6801s were likely for testing for cars, though it is unclear if Chrysler actually used the 6801 in their vehicles as ECUs from the mid-80’s all seem to be running the 6803 and 6805 MCUs.  Maybe if I find an early 80’s Chrysler I’ll tear out the ECU and find out.

 

November 24th, 2017 ~ by admin

New Test Board Available for Sale: Intel 3002 Bit-Slice Processor

3002 Test Board

We have released a simple (its our least expensive board yet) Test Board for the Intel 3002 Bit-Slice Processor.  The Intel 3000 bit-slice processor family was introduced in 1973 and were made on a  Schottky Bipolar process. The 3002 series was also second sourced by Signetics, Siemens, and Intersil, and clones were made by the USSR and Tesla  (Czech).  The 3002 CPE is a 2-bit ALU and register file that can perform logical and arithmetic operations, left/right shifting and bit/zero value testing. The 3002 also includes 11 registers (R0-R9, T), an accumulator and a Memory Address Register (MAR). The 3002 CPE elements execute micro instructions generated by the 3001 Microprogram Controller Unit (MCU) based on micro code stored in PROM.
Its only $69.95 (including FREE shipping worldwide)

Order it on the 3002 test Board page.

In other related news, we are also developing a test board for some other BSP. Hopefully we’ll have a single board (with expansions) that can handle AMD 2901/03/203 and MMI 6701 processors

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