October 15th, 2014 ~ by admin

Has the FDIV bug met its match? Enter the Intel FSIN bug

Intel A80501-60 SX753 - Early 1993 containing the FDIV bug

Intel A80501-60 SX753 – Early 1993 containing the FDIV bug

In 1994 Intel had a bit of an issue.  The newly released Pentium processor, replacement for the now 5 year old i486 had a bit of a problem, it couldn’t properly compute floating point division in some cases.  The FDIV instructions on the Pentium used a lookup table (Programmable Logic Array) to speed calculation.  This PLA had 1066 entries, which were mostly correct except 5 out of the 1066 did not get written to the PLA due to a programming error, so any calculation that hit one of those 5 cells, would result in an erroneous result.  A fairly significant error but not at all uncommon, bugs in processors are fairly common.  They are found, documented as errata, and if serious enough, and practical, fixed in the next silicon revision.

What made the FDIV infamous was, in the terms of the 21st century, it went viral.  The media, who really had little understanding of such things, caught wind and reported it as if it was the end of computing.  Intel was forced to enact a lifetime replacement program for effected chips.  Now the FDIV bug is the stuff of computer history, a lesson in bad PR more then bad silicon.

Current Intel processors also suffer from bad math, though in this case its the FSIN (and FCOS) instructions.  these instructions calculate the sine of float point numbers.  The big problem here is Intel’s documentation says the instruction is nearly perfect over a VERY wide range of inputs.  It turns out, according to extensive research by Bruce Dawson, of Google, to be very inaccurate, and not just for a limited set of inputs.

Interestingly the root of the cause is another look-up table, in this case the hard coded value of pi, which Intel, for whatever reason, limited to just 66-bits. a value much too inaccurate for an 80-bit FPU.

October 11th, 2014 ~ by admin

Why the Zilog Z-80′s data pins are scrambled

Zilog Z80A CPU -1978

Zilog Z80A CPU -1978

Ken Shirriff has an excellent write up about the Zilog Z80 and why its pin-out, specifically the Data lines, is a bit convoluted.  Rather then being in order (such as D0-D7) the original Z80 is D4,D3.D5,D6,D2,D7,D0,D.  Its functional but its not pretty and can lead to some interesting PCB layout issues.  Ken uses data/imaging from the Visual6502 project to look at the on die reasons for this.  Essentially it came down to saving die space. there literally was not enough room to route the data connections within the confines of the die size.  Keeping the die size small allowed Zilog, and its many second sources), to keep prices down.  In the early days Zilog contracted Mostek to make much of their processors, so die size and the associated cost were a big issue.

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Research

September 27th, 2014 ~ by admin

Apple A8 Processor: A smaller, faster A7

Anandtech and Chipworks deconstructed an Apple A8 processor, the hear of the new iPhone 6.  By their analysis it is not a radical departure from the A7.  It includes a slightly upgrade, but still quad-core, GPU, and an enhanced dual core ARM processor.  The focus here is clearly on battery performance rather then sheer speed.  Perhaps most interesting is the move from Samsung’s 28nm process to TSMC’s 20nm process (Being made by TSMC will hopefully put to rest the rumors of an Apple/Intel tie up once and for all.).  This results in lower power, a smaller die area, and, assuming yields are on par, a lower cost per chip.  Clock speed appears to be close to the same as the A7 at around 1.3GHz, with most performance improvements being architectural. It would appear to be the smallest improvement in the Apple A series, certainly since the A4->A5.

Considering the incremental improvement from the A7, one can only imagine what Apple has in mind for the A9 which is no doubt well under development.

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Museum News

September 27th, 2014 ~ by admin

National Semiconductor: The COP before the COPS

National Semiconductor MM5782N - 400KHz 1976

National Semiconductor MM5782N – 400KHz 1976

In August we detailed the COP2404 and the COP400 line of 4-bit microcomputers by National Semiconductor.  This NMOS design originated in 1977 and was made for over 30 years.  It, however, was not the the first COP line of National Semiconductor.  In fact the COP400 family was referred to as the COPS II for a brief period in the 1970′s.  If the COP400 was the second in line then what was the ORIGINAL COP microcomputer?

That would be the COPS I of course, better known as the MM5781/2 and its derivatives, the MM5799, MM57140 and MM57152.  These microcomputers were released in 1976 and were made on a volume PMOS process.  They were designed to be inexpensive and simple to use.  The design of the 5781/2 actually started with the MM5734 which was a single chip accumulating calculator chip.  The differences are not as big as one may think.  A multi-function calculator with memory needs an ALU, registers, ann accumulator and instruction decoding, as well as very limited memory and fairly extensive I/O (to run the display and read inputs from the keyboard).  National saw this as an opportunity to capture a bit of the low-end market.  They already had the IMP-16 for their high end, the SC/MP for the mid range, as well as second sourced Intel MCS-4 and MCS-80.  What they lacked was something to compete with the likes of the WD1872 and the TI TMS1000 series as well as the rise of the Japanese 4-bit solutions from NEC, Toshiba and Sanyo.

The 5781/2 was a 2 chip solution, together they formed a microcomputer.  The 5781 contained the program ROM (2048 x 8 bits), as well as the program counter and some control logic.  The 5782 was contained the full ALU, the accumulator, the instruction decoder, and 160×4 bits of RAM.  It could execute 33 different instructions.  Clock speed was 70-400KHz and was provided by an off-chip oscillator.

National Semiconductor MM5799 - Single chip COPs

National Semiconductor MM5799 – Single chip COPs

National combined the 5781/2 into a single 28 pin chip called the MM5799.  It contained all the logic of the 5781/2 but with a smaller amount of RAM (96 x 4 bits) and ROM (1500 x 8 bits). Clock speed remained the same but the instruction set was expanded slightly to 41 instructions.  Two other versions were also made that had more extensive I/O.  The MM57140 which had build in LED drivers, and the MM57152 which was the same, but had built in fluorescent display drivers (this was the 1970′s after all). The ’140 and ’152 had 36 instructions 55 x 4 bits of RAM and 630 x 8 bits of ROM. Maximum clock speed was also reduced to 280KHz.

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September 5th, 2014 ~ by admin

MasPar: Massively Parallel Computers – 32 cores on a chip

MasPar PE3232 - 32 12.5MHz 32 bit Processing Elements - 1992

MasPar PE3232 – 32 12.5MHz 32 bit Processing Elements – 1992

In the 1980′s DEC researchers were designing a supercomputer based on the Goodyear MPP from 1983.  Jeff Kalb was in charge of the division of DEC involved in this work.  The original Goodyear MPP wa based on a 1-bit processor element (PE).  DEC increased that to a 4-bit PE as well as increased the connectivity between PE’s.  When DEC decided to not commercialize the supercomputer design Kalb left (with DEC’s blessing) to start a company of his own that would.  Thus the creation of MasPar in 1987.

MasPar derives its name from the product it sought to create, a Massively Parallel supercomputer.  These type of computers, also referred to as vector processors are SIMD machines, Single Instruction, Multiple Data.  They perform the same operation on a very large set of data.  SIMD instructions are now found on most all desktop processors, where they can greatly speed up processing of multimedia.  In the late 1980′s there was several companies making such MPP computers.  Perhaps the most famous was Cray, but there was also Thinking Machine’s Connection Machine, Intel’s Paragon (i860 based), nCUBE’s hypercube, Meiko Scientific’s CS-1 (Transputer based) and several others.  Such systems cost from upwards of $100,000 each so sales were not vast, typically companies sold a few hundred to a few thousand systems.

MasPar’s first design, the MP-1 was based directly on the research done at DEC.  Each processing element contained a 4-bit ALU, a 1-bit logic unit, a 64/16 (mantissa/exponent) unit for handling floating point.  Each PE also had 48 32-bit registers.  There were designed as a 32-bit RISC processor, which means, that with the 4-bit ALU, any ALU operation would take at least 8 cycles.  This was considered acceptable in a MPP type system.  Each custom VLSI CMOS MP-1 chip contained 32 individual PE’s.  They were made on a 1.6u process and contained 400,000 transistors.  Clock speed was a fairly low 12.5MHz but this allowed the chips to be air cooled with no special cooling systems.   They were packaged in an inexpensive 208 PQFP, nothing special needed due to the low heat dissipation.  A 1024 PE board (32 chips) dissipated only 50 Watts, and an entire 16k processor system dissipated less than 1,000 watts.

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August 30th, 2014 ~ by admin

Improve Technologies Make-it 486 – 286 Upgrade

Cx486SLC/e-33MP Based Improve Technologies Make-It 386 for a 286

Cx486SLC/e-33MP Based Improve Technologies Make-It 386 for a 286

Improve Technologies (IT) was a company that existed from 1991-1997.  They were one of the many (to include Cyrix, Evergreen, PNY, Gainbery, etc) that made processors for upgrading 286, 386 and 486 computers.  Processor upgrades are no longer commonplace, becoming nearly non-existent (except for such things as 771 to 775 adapters).  Today computer hardware has become so inexpensive that upgrading more often just consists of purchasing a whole new computer, or at least new motherboard, RAM, and CPU, all at a price of a few hundred dollars.

In the early to mid-90;s however, a computer system cost 2-$3000, so replacing it every few years was not financially viable for many people.  Thus processor upgrades, they were designed to replace a CPU with the next generation CPU (with some limitations) at a price of a few hundred dollars.

In 1976 TranEra was founded in Utah. TransEra is an engineering solutions company, they are built on seeing a technological problem, and engineering a solution, whatever that may be.  They began by making add-on for Tektronix test gear and HP-IB interface equipment.  In 1988 they released HTBasic, a BASIC programming language (based on HP’s Rocky Mountain BASIC) for PC’s.  This is what TransEra became perhaps best known for, as they continue to develop and sell HTBasic.  It was TransEra who developed the Improve Technologies line of upgrades.  They saw a problem, and engineered a solution.

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CPU of the Day

August 25th, 2014 ~ by admin

National Semiconductor COP2404 – Dual Core Processor from 1982

National Semiconductor COP2404N - Dual core processor

National Semiconductor COP2404N – Dual core processor

National Semiconductor introduced the COPS series of 4-bit processors in 1977.  COPS came from National’s calculator line of chips, and for a short time were known as Calculator Oriented Processors, however this was rapidly changed to Control Oriented Processor System (COPS).  These 4-bit microcontrollers, as their name suggests, were for controlling various consumer devices.  They were used in all sorts of devices from game consoles, to dishwashers.  In the early 1980s National began producing them in CMOS versions, and in 1988 they extended the line to 8-bit (the COP8 family).

COP2404 Block Diagram - 2 Cores with shared memory. - Click to enlarge

COP2404 Block Diagram – 2 Cores with shared memory. – Click to enlarge

In 1981 the COP2404 (and 2440) were announced, with availability beginning in 1982.  The COP2404 was on the top end of the COPS line, it was found that some real time control operations were better served by 2 microcontrollers, so why not design 2 into one.  The 2404 is a dual core processor, with two complete COPS404 cores on one die, sharing I/O and RAM. (The 2440 also included ROM).  True to multi-core form, the memory was shared, meaning the processors could work independently or pass data to each other, including task handoffs if the programmer so desired.  This wasn’t implemented in hardware, but it wasn’t forbidden either, meaning a programmer could do some pretty complicated task management with the dual CPU cores.

The 2404 was packed in a 48 pin PDIP, and was designed as a development device for use with external program memory (EPROM typically).  Production devices were the 2440 (40 pin) 2441 (28 pin) and 2442 (24 pin) which all had 2K of ROM on die.  All included 160×4 bits of RAM and had an instruction cycle of 4usec (using a 4MHz clock, as each instruction took 16 cycles).  They were manufactured on a 3-micron NMOS process (originally, likely shrunk over time).

As technology progressed it became easier to handle multiple real time tasks with a single, faster controller, with good hardware interrupt handling, but for a time, their was a dual-core processor.  The COPS series continued to be sold by National until 2011, when they were bought by Texas Instruments.  While no longer actively marketed, several members of the COP8 line are still being sold.

August 15th, 2014 ~ by admin

Four-Phase Systems AL1 Processor – 8-bits by Lee Boysel

Four-Phase Systems AL-4 - 1000+ gates 8-bits

Four-Phase Systems AL-4 – 1000+ gates 8-bits

In today’s tech economy there are companies that serve as incubators for startups, such institutions as Y-Combinator and Techstars entire purpose is to help develop emergent tech companies.  In the 1960′s there was also tech incubators, perhaps the best known is Fairchild.  The difference is that Fairchild was not designed to be an incubator, nor were they trying to be.  The bureaucracy of such a large corporation allowed many engineers in somewhat marginal positions to work extensiely on projects of their own. Projects that perhaps were not directly beneficial to Fairchild, but close enough related to slip under managements noses.  Many of the ‘great’ semiconductor companies were started by former Fairchild employees, Robert Noyce, co-founder of Intel, being perhaps the most famous.

Lee Boysel started work at Fairchild in 1966 after working at several other companies semiconductor departments.  Boysel had one main focus, MOS.  MOS (Metal-Oxide-Semiconductors) were very new in the 1960′s and their potential was not well understood.  Most IC’s were designed using Bipolar technology but Boysel saw the potential of MOS and worked at Fairchild to perfect its processes.  He designed a 256-bit RAM in MOS< as well as an 8-bit full adder, as well as the first MOS IC with over 100 gates.  None of these designs were of great commercial success, but that was Fairchild’s problem, not Boysel’s. Boysel was building the foundations for his greater plans, plans that would be realized only after leaving Fairchild.

Boysel left Fairchild in 1968, to build a new company known as Four-Phase Systems.  Four-Phase was named after the 4-phase clocking system used in the MOS logic Boysel had designed.  Boysel’s goal was to build a single chip computer using MOS and use it to power systems to rival the likes of Data General and IBM.  Initial funding of $2 million was provided, somewhat ironically, by Corning Glass works, who also owned a large portion of Signetics.  Initial production of Boysel’s designs was by yet another Fairchild incubated startup known as Cartesian inc.  Cartesian was offered foundry services that duplicated Fairchild;s MOS process.  This saved Four-Phase from having to build there designs for a completely new process.

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August 13th, 2014 ~ by admin

What’s Missing?

Four-Phase Systems: 1969-1981

Four-Phase Systems: 1969-1981 (click to enlarge

What’s Missing from this Four-Phase Systems family portrait?  Hopefully the lost member arrives this week.  Anyone remember Four-Phase?

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Just For Fun

August 10th, 2014 ~ by admin

An Interesting Fujitsu MCM Pentium Module

Fujitsu MRN-3545 (100) 100MHz Pentium with no L2 Cache

Fujitsu MRN-3545 (100)
100MHz Pentium with no L2 Cache

We have seen Fujitsu MCM Pentiums before.  120MHz, 133MHz 150MHz and MMX ones.  One is pictured in the article on the MicroModule Systems Gemini here.  The 100MHz module is similar, though it is missing the L2 cache tag RAM (256 kbit chip on the top of the package) as well as the 2 cache RAM chips normally installed on the backside of the module.  It would appear that Fujitsu offered these modules with the cache being optional.  There was a 133MHz version (MRN-3548) with cache, and one (MRN-3549) without cache.

These processors were typically used in environmentally challenging environments.  Panasonic famously used them in their ToughBook CF25, the beginning of a line of highly durable laptop in 1996.  Some of these applications were sealed environments, they did not have vents, or active cooling.  This obviously  makes cooling a challenge.  Removing the L2 cache, while causing a significant hit in performance, would alleviate some of the heat generation.

We consider L2 cache to be essential, but many applications do not require it.  Intel infamously removed the L2 Cache completely from the first Celeron processors and while they worked, they were not particularly competitive performance wise.  When competing against wind, rain dirt, and droppage? L2 cache may not be so important