Introduction

In this article, I would like to recall how the history of high-end computers or High-End Desktop PC (HEDT) began, what we now have in this segment, and what awaits us in the near future.

Until a certain point in time, the computer market for personal computers was not divided into subcategories. There was the concept of a personal computer, where its main criteria were: performance and cost. The higher the performance, the more expensive such a PC was. There was and still are ‘Workstation’ class PC’s but these are really more of a Business class (think CAD or Video editing) then what you would buy for your house. The problem of insufficient performance was solved for a very long time with the help of overclocking and it would seem that this order of things suited everyone.

If you want a faster video card or processor, buy the Top model. Until a certain point in time, everything was like that, but at the beginning of the 2000s, processor manufacturers realized that there was a certain group of buyers who were willing to pay more. Then they were called “enthusiasts”, and now they have been renamed “gamers”. Since 2003, Intel, in unison with AMD, has been releasing their processors for wealthy enthusiasts. The first processor model from “blue” was the – Pentium 4 Extreme Edition with a clock frequency of 3.2 GHz and a very nice price of $999 (A Celeron of that era was around $100 for 2.5-2.8GHz).

Thus, in this processor model, a beautiful and memorable cost, a defiant name and technological sophistication, the roots of which go deep into the server segment, are combined. The owners of the “extreme desktop processor” already considered themselves a completely different caste, and no overclocking of the older processor model could give an ordinary user the performance that an enthusiast had, and after all, extreme processors were also overclocked.

At first, AMD generally went the other way, a special separate platform was created for enthusiasts, where processors with their own separate socket were installed. Thus, the segmentation of the personal PC class took place at the physical level. We are talking about AMD Athlon 64 FX processors, and to be more precise, about the first model of this family – AMD Athlon 64 FX-51. I would call them timeless classics, still using a ceramic package, a separate socket, and special registered DDR-SRAM memory.

The release of these desktop processors for enthusiasts also marked the beginning of a new 64-bit era and changed the leaders of the processor industry. The yellow jersey of the leader shone on a green “background”, and Intel moved into the camp of catching up. As revenues and the image component of users and enthusiasts grew, marketers and simple engineers did not sit idly by. Performance is never enough (although it seems to me that for the last 5 years it has definitely been enough in any products of the middle-end segment) and something had to be offered to enthusiasts who were willing to pay even more. I suppose that such wealthy enthusiasts are now called creators or a close meaning of this term.

HEDT from Intel

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Intel released the i8755 in 1976, the i8755A in 1977 (with better compatibility with the 8085A and 8086/8). The Intel 8755 is an UV- erasable and electrically reprogrammable ROM (UV-EPROM) and I/O chip. The EPROM portion has 16 384 bits, organized as 2048 words by 8 bits. The I/O portion has two general purpose I/O ports, each I/O port is individually programmable as input or output.  These were essentially a combination of the 8255 PIO and the 2716 EPROM on a single die/package. These were made on a NMOS process.

Intel C8755-8 – 1977

Intel C8755A – 1979

NEC D8755AD -1981

Toshiba TMP8755AC ’83

NEC and Toshiba released similar microcircuits behind Intel. Basically, the microcircuit was intended to work together with the 8085A microprocessor. It differs from its predecessor i8080A in that it has a multiplexed data and lower address bus. The standard three-bus architecture of the microprocessor system is obtained by multiplexing with the help of an additional external register. In this register, the low byte of the address is fixed by the special output signal of the microprocessor.

Intel 87C75PF Engineering Sample – 1988

By 1988, the 8755A was obsolete and Intel released the 87C75 instead (see article on the CMOS 87C75).

Novosibirsk IM1821VM85A – 1989

Around this time, the production of an analogue of the i8755A, the 573RF10 microcircuit, began in the Soviet Union. Why start producing a microchip that the world electronics leader is changing to a more advanced one? The fact is that at the beginning of 1988, the production of IM1821VM85A began in the USSR. This was a radiation hard analogue of the CMOS i80C85A. It was with it that the 573RF10 was supposed to work.

K573RF10E (gold pins) 1990

KM573RF10 – Gold ’92 / tin pins ’93

The chip is made in a 40-pin side-brazed ceramic DIP. Supply voltage +5 V. Programming voltage +21 V. It was produced at the Vostok fab in Novosibirsk on a CMOS process (to match the 80C85A).

Unmarked 573RF10

The 573RF10 is the only CMOS chip in the 573 series.

573RF10 die – single memory cell – radiopicture.listbb.ru

Intel 8755A die – 2 memory cells – cpu-galaxy.at

It is noticeable to the naked eye that the 573RF10 is own Soviet development. The 573RF10 and i8755A dies are completely different. The i8755 has two memory arrays clearly visible, while the 573RF10 has only one.
It must be said that the application of the 573RF10 chip was not wide enough. And in general, the idea did not take root. The next obvious step in evolution was the combination of a microprocessor, ROM and RAM, input-output ports in one chip which was frequently done on the MCS-48 and MCS-51 series MCU’s which were also being produced in the Soviet Union at the time.

Written by guest author Vladimir Yakovlev
Edited/Formatted by John Culver – The CPU Shack Museum
Pictures – The CPU Shack Museum and others

This article is about memory chips manufactured by one of the entities – the leader of the electronic industry of the USSR – Angstrem. As you know, the Soviet Union ceased to exist in December 1991. We restrict ourselves to the development period of the considered memory chips produced at Angstrem, the end of 1991. Let’s make an attempt to track how the capacity of memory chips grew, how technologies were improved that allowed the Soviet Union not to let the world leaders in electronics go far from itself at that time. A small example: Angstrem’s Dynamic RAM 4K went into mass production in mid-1975, Intel introduced its own in 1974. Intel launched a 16K DRAM in 1977, and Angstrem released its counterpart in 1978.

Angstrem Headquarters

Angstrem was established in June 1963 in Zelenograd (outside of Moscow) as a pilot plant in conjunction with the Scientific Research Institute of Precision Technology. At Angstrem, new technologies for the production of microelectronics were developed, and pilot batches of new microcircuits were also produced. The debugged production technology was then transferred to other enterprises of the USSR and countries of Eastern Europe.
The development and manufacture of memory chips was one of the main activities of Angstrem. It was on them that new semiconductor structures and production technologies were more effectively worked out, and the stability of obtaining finished products is considered in world electronics as a sign of technology ownership. It’s relatively easy to make a small batch of good chips, it’s hard to make a process whereby a large amount of chips can be made and be reliable. It was the very low chip yield percentage that played a cruel joke on Angstrem when mastering the production process of the DRAM 565RU7 chip.

SRAM

In 1966, Angstrem created the first MOSFET in the USSR, which was the first step towards the strict goal of creating CMOS integrated circuits. The first CMOS microcircuit, created in the Soviet Union in 1971, was the 16-bit Angstrom matrix of memory cells 1YaM881.The supply voltage is 6 volts instead of 5 volts, like the rest of the chips in this series.

1YaM881 – 1972

The next in a series of static RAM chips was the CMOS K561RU2 (K564RU2), released in 1976. 564 series of chips is a “military” analogue of the 561 series. In these series, there are several dozen microcircuits. The chip has an organization of 256 words by 1 bit.

561RU2 die – 16×16 256bit matrix clearly visible – The image is taken from the site https://radiopicture.listbb.ru/ with the permission of the author.

It contains 2067 integral elements. Supply voltage is 3-15 volts. It’s an analogue of CD4061A.  It should be noted that in most cases ‘analogue’ means similar to, not an exact copy or exactly compatible.  The USSR did make some compatible IC’s, but they mostly made stuff that was similar, but built to their own specifications/needs.

K564RU2A -1978

K561RU2 -1979

The package of the K561RU2 chip is wider than the standard packages of this series.

K565RU2 -1979

The K565RU2 static RAM chip was manufactured using NMOS technology. Chip capacity was 1024 bits (1024×1). Contains 7142 integral elements. An analogue of Intel 2102A, developed in 1974. K565RU2 appeared in 1977. It was originally designed to be placed in a ceramic package, but later, in order to reduce the cost of production, the dies began to be packed in plastic packages.

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When Apple bought P.A. Semi back in 2008 it was the beginning of the era of the iPhone, and their was much speculation as to why Apple was buying a company that made low power high performance PowerPC processors.  Especially since the iPhone ran on ARM and the Mac had moved from PowerPC to x86.

P.A. Semi PA6T-1682M

P.A. Semi was started in 2003 by Daniel Dobberpuhl (who passed away in 2019).  Dobberpuhl was one of the truly greats of microprocessor design, with a career starting at DEC on the T-11 and MicroVAX, before helping DEC transition to the Alpha RISC design (21064).  It was Dobberpuhl who started the design center in Pal Alto (where P.A. Semi would later take its name from) that designed the DEC StrongARM processor.  A processor that was later purchased by Intel and became the XScale line of ARM processors.

After Intel bought the StrongARM line, he then helped start SiByte, making MIPS based RISC CPUs, and continued to do so when SiByte was purchased by Broadcom. So when he started P.A. Semi it was less about PowerPC and more about RISC, PowerPC just happened to be the architecture they chose to use.  The design team had extensive experience on a variety of CPU architectures, including SPARC, Itanium, and the early Opterons.  You can see why this acquisition was so attractive to Apple.

PA6T block diagram

In the few years (2003-2008) from when P.A. was founded to when Apple took them over, they did design, market, and sell a PowerPC processor line called PWRficient based on what they called the PA6T core.  The PA6T-1682M was a Dual core PowerPC processor (the 13xxM was the single core version) with each core running at up to 2GHz with 64K of L1 Instruction cache and 64K of L1 Data cache.  They were fab’d on a 65nm process by TI and ran at 1.1V.  The L2 cache was scalable and shared amongst the cores.  In the 1682M this was a 2M 8-way cache with ECC.  One of the most useful features was their clock stepping.  They could drop to 500MHz at only a few watts per core, and then back up to the full 2GHz in 25us.

AmigaOne X1000 (made by Aeon) PA6T-1682M

The PA6T was only on the marked for a few months (from the end of 2007 to April 2008) before Apple bought them for $300 million, but in this time P.A. Semi had numerous design wins.  Amiga selected it for use in the AmigaOne X1000 computer.  The AmigaOne did not hit market until 2011, which means that while P.A. Semi was bought and completely under control of Apple, they still continued to make, support, and supply their previous customers with the 1682M CPU.  Certainly Amiga wouldn’t be big enough to push Apple to continue making a chip?

They were not, but others were, and the PA6T was such a great processor that it had been selected and designed in to many computer system used by US Defense contractors, and if anyone doesn’t like change, its Defense contractors, so with some prodding by the US Dept of Defense Apple continued to make (or rather have TI make) the PA6T processors.  Curtis-Wright had designed the PA6T into their new CHAMP-AV5 DSP VME64 board, which was used for signals processing across numerous military applications.  They also also used the PA6T (at 1.5GHz) in the VPX3-125 SBC. Themis computers, NEC, Mercury and others designed in the PA6T. Extreme Engineering, another maker of PA6T based boards, referred to the design as ‘ground breaking.’

Extreme Engineering XPedite8070 SBC

It would have been interesting to see what P.A. Semi could have achieved had they not been gobbled up by Apple.  Clearly we see the results of the talent of the P.A. team in what Apple was able to accomplish with their A-series processors, but clearly P.A. had something special for the PowerPC architecture as well.

AlphaServer GS60 and GS140

The DEC TurboLaser 8200/8400 was a series of high end Windows NT compatible servers/workstations introduced in 1995.  After DEC was sold to Compaq (in 1998) the 8200/8400 were upgraded from the EV5/EV56 (21164/21164A) to the 21264/21264A (EV6/EV67).  Compaq wasn’t as bold with code names it seems so instead of being referred to as the TurboLaser they were simply called the TL6.  The machines themselves were also renamed from the 8200 to the GS60 and the higher end 8400 to the GS140.  GS referring to ‘Global Solution’ to reflect Compaq’s international marketing of the computers.  The GS60 was the lower end rackmount model supporting up to 6 CPUs and 12GB of RAM and the GS140 full cabinet model supporting up to 14 CPU and 28GB of RAM.  Both could be configured with either 21264 525MHz CPUs with 4MB of B-cache each or 700MHz 21264A CPUs with 8MB of B-cache each.  The 21264A added support for writeback cache, as well as its faster speeds and some new instruction set extensions.  Initially availability of these systems was in late November of 1999, coinciding with the release of the 21264A CPUs.  By the time of their release Alpha support for Windows NT was lagging, so most if not all systems were sold with Tru64 UNIX or OpenVMS OS.

The GS60/140 were large cases similar to a rackmount system but self contained.  The processor modules for them contained a pair of CPUs, the cache for the CPUs and the entire chipset.  They connected to the main computer with a very large connector that provided power (48VDC) as well as all the Memory/IO and clock signaling.  This was referred to as the TLSB (TurboLaser System Bus).   The fastest of these was the KN7CH (also known as the E2067-DA) which had dual 700MHz 21264A processors with 8MB of Cache each.

DEC KN7CH 6/700 Processor Board

This processor board is quite interesting, its a rather early board (PLDs are dated March of 2000) and the pair of Samsung 21264A processors are dated 9944, these are some of the very first production 21264As.  Also of interest is that these Samsung CPUs are 733MHz models (KP21264A-733UCN).  The 21264A was to be made in 600, 650, 667, 700, 733, and 750MHz versions, though I have only actually seen 667 and 733MHz versions.  Making only 2 speed grades of the processor would greatly simplify testing and logistics, and with a rather limited customer base, there wasn’t a clear marketing need to make so many different speeds, these were not CPUs that were generally available outside of OEM use.  These servers were also designed to be high reliability systems, running a 733MHz rated CPU at 700MHz would increase reliability by decreasing heat related wear and tear.

Build Sheet for a 8-Node GS140 with Eight 6 CPU GS140 6/700 Systems. Each with 12GB of RAM. A nice $9 million system

The entry price for the AlphaServer GS60 with 4 GB of memory was $199,990 ($340,000 in 2022). The AlphaServer GS140 system price started at $399,400 ($680,000 in 2022). These were very expensive systems.  One look at the processor board shows what that kind of expense gets you, a whole lot of gold.  Its hard to find another computer system built in 2000 that has 9 gold/ceramic chips on each processor board.  A single dual processor board was $45,000 ($76,000 in 2022USD), and each 4GB of RAM was another $49,000.  One can easily see how such a system could quickly cost several million dollars.  Each of these boards cost as much as a really nice car!  Lets look at what that $45,000 gets you

Top Row (L->R) SWI, Alpha 21264A, SWI – Bottom Row: TDI, TDI, TCC, TDI, TDI

2x KP21264A-733UCN. Each 21264A chip has a separate address and data bus for the B-cache and system operations. The 21264A chip has a 64-Kbyte instruction cache and a 64-Kbyte data cache.  These are made by Samsung on a 0.25u process and dissipate 85Watts at 2.0V.

20x IBM SRAM Cache Memory: 8-Mbyte ECC L2 cache per CPU made using 16x IBM 0418A81QLAA-4 512Kx18 8Mb ECC SRAM chips and 2x 128Kx36 / 2x 256×18 for the TAG RAM

2x DEC 21-47306-01 SWI: Two swizzle (SWI) chips receive data from the 256-bit wide DLSB (the DEC Local Bus) and pass it to one of the CPU chips over the 64-bit wide data interface bus.  These are located on either side of the pair of CPUs.

4x DEC 21-47307-01 TDI: Four TurboLaser Data Interface (TDI) chips receive data from the TLSB (the main system bus that connects all cards in the system) and pass the data over the DLSB to the two SWI chips.  These are the outer 4 chips on each end of the row of 5 gold chips on the bottom.  Each one handles 64-bits of the 256-bit TLSB.

1x DEC 21-47315-01 TCC: The TurboLaser control chip (TCC) takes commands from both CPUs and issues them to the TLSB. It also controls all data movements through the TDI and SWI chips. This is the center chip between the pairs of TDI chips.

2x AMD AM29F080DB-90EC: 5V 8Mbit Flash for the system firmware

4x Galaxy Power DC-DC Converters.  These regulate down the 48VDC supplied by the systems redundant power supplies to the voltages needed for the board.  There is a pair of 2.2V 7A converters for the CPUs, and a 7A 3.3V converter for all the I/O.  There also is a smaller 2A converter of unknown voltage (likely 5V).

Pair of Samsung KP21264A-733 Processors surrounded by cache chips

The TurboLaser line was replaced in 2002 by the WildFire servers (GS80, GS160 and GS320) which upgraded the CPU support to 32 21264Cs with 256GB of RAM.  Unfortunately by this time Compaq had merged with HP and the combined server line was a bit cluttered, having Alpha, PA-RISC, Itanium and Xeon based systems.  The Wildfire and its Marvel follow on were the end of the road for the Alpha.  Unfortunately the same thing happened with the PA-RISC and Itanium (ok maybe not so unfortunately with Itanic) as well.  The days of boards full of golden RISC are past, replaced by BGAs with enormous heatsinks.

GammaChrome XM18 – Engineering Sample

Recently I got in some very nice S3 GammaChrome GPUs.  The GammaChrome was S3 (owned by VIAs) follow on to the DeltaChrome and included support for such things at PCI-E.  The S18 (Code name Brooklyn) supported speeds of up to 500MHz and was made on a 130nm process by TSMC.  S3 also made a mobile version of the S18 called the XM18 (Code name Metro MPM) in 64MB and 32MB versions.  Clock speed on these was around 350MHz (memory on the samples I have is 350 so core should be similar).  The XM18 was packaged on a MPM (Multi Package Module) with 2 RAM chips and the GPU mounted on a small chip size BGA with around 800 balls.  This is very similar to how ATI packaged some of their mobile GPUs (like the Mobility Radeon 7500 and 9600).

HP 93000 (from HP Brochure)

So how do you test one of the XM18 Engineering Samples? Or any large scale chip for

86C813 ES Gamma Chrome XM18 ULP MPM64

that matter?  With Automated Test Equipment.  ATE systems are designed to rapidly test various chips to verify their design/performance before they go into full production (or to test samples of production ones).  The HP/Agilent 93000 (spunoff as Verigy in 2007 and acquired by Advantest Corporation in 2011) was introduced in 1999 to handle such testing, and at the time was rather revolutionary.  Previously most test systems used a simple test head that would mount the chip to be tested, with all the processing and customizations being contained in the main test machine.  This worked fine for a single design, but to test multiple chips got pretty expensive.  HP moved the testing to the test head directly, interfacing to the target chip via a large PCB.  This way changing chips only required updating the test program, and changing out the PCB.  Design changes required reworking a single PCB, rather then the entire test machine.

HP 93000 Test Head – Notice the 16 groups of pins (some covers and some mangled in this old sale photo)

The 93000 was the first ATE that achieved (on its low end (200Mbps) a cost of $1000/pin tested, and on the high end, test speeds of up to 1250Mbps (for the P1000 version, at a cost of $6-7000 per pin).  The XM18 has around 800 pins, half are probably power/ground so 400 some odd testable pins, in a mid range HP 93000 and you see these systems were not inexpensive. Well over a million dollars for a midrange system.

GammaChrome XM18 – Metro MPM Test Board

To use such a system the chip to be tested would be mounted on the test board, usually with a BGA socket.  This board breaks out all the various connections of the chip to 16 sets of contacts, which the probe head of the HP 93000 made contact with using spring loaded contacts.  The board is then clamped down and tests are run.

Connection List

These boards are very very large, each one is 17x23inches (43x58cm) and 5mm thick.  They weigh about 7lbs (3.1kg) as well.  They got used a lot and need to be rather robust and durable.  You can see the boards are marked with tables of all the connections, and where they are brought out to.  Useful information about what supporting equipment is need (sockets and stiffeners etc) is marked on the board as well.

Back of board. Notice all the capacitors, a crystal, and a series of 5VDC reed relays (the red devices)

These boards appear to be a ‘static’ type item, but they do require adjustment, notice the markings that say not to use this board, it needs recalibrated.  Looking closely at the board you can see capacitors have been removed/replaced, and many of the capacitors have felt tip marker markings on them.  Keeping the capacitance and inductances at their proper values 9and matched, considering the long trace lengths) would be a very important thing.

S3/VIA Matrix Test Board. The Matrix was the code name for the GammaChrome S14/S19

These test boards are from 2006, the 93000 systems are still being used today in upgraded form (now called the V93000) to test SoCs and other chips.  As chips have gotten more and more complex, faster, and with larger pin outs, test equipment continues to grow ins peed, and cost as well, but is an essential part to the process of designing, producing and supporting a successful GPU or CPU.

C5M – Ezra-T Prototype Pathfinder – PGA370

Most are familiar with the history of VIA so we won’t dive extensively into that but a quick summary is in order.  VIA was founded in California in 1987 before moving to Taiwan, and previous to 1999 was well known for making chipsets and other support chips for computers.  In 1999 VIA bought both Cyrix (from National Semiconductor) and Centaur Technologies (from IDT, who made the Winchip series of processors.

These purchases did two main things for VIA, it first gave them access to the x86 architecture, and it gave them legal leverage to continue down the x86 road.  Cyrix possessed a license to the P6 processor bus (through a cross licensing with Intel) that was good until 2006.  This allowed VIA to make what became the Centaur based CyrixIII/C3 processor on the P6 based Socket 370 platform. These are the processors and socket we are most familiar with for VIA CPUs.  With clock speeds of 466-1.2GHz and eventual support for the Tualatin based boards these chips were the most ‘public’ facing CPUs.  VIA also of course made many BGA versions, used in ITX form factor, and other mini type systems.

CNA – Isaiah – Interestingly using the old Pentium III-M pin out

The VIA designs, despite originally being called ‘CyrixIII’ were all based on the Centaur designed core.  Intel, as was its custom, sued VIA in 2001 asserting patent infringement, which it is likely VIA was expecting.  As with the case of Intel and Cyrix, VIA countersued, asserting Intel was infringing on patents VIA had acquired with the Centaur deal.  In 2003 a settlement was reached that included a 10 year patent cross license between Intel and VIA and allowed VIA to continue to make x86 compatible processors (extended in 2013 by 5 years until 2018(.  The deal also granted VIA a 4 year (with an extra optional year) license to continue to make chipsets compatible with Intel processors (they had originally signed a deal in 1998 to allow VIA to do so. This is how we continued to get VIA chipset based motherboards for Intel processors.  The deal also added a small detail that leads to todays discussion, it granted VIA a 3 year grace period to continue making bus and pin compatible processors up through 2006.

C5J (Left) and C5R (Right) – Banias Compatible Pentium M pin out

This last part is interesting, the fact that it was a grace period means it reflected what VIA was currently doing, not what they were planning to do in the future.  The obvious example here is the C3 line on Socket 370 using the P6/Tualatin bus, but that was pretty old news in 2003 so what was VIA working on?  CPU’s on more modern sockets of course, namely Socket 479 (mPGA479M) used by the Pentium-III-M (Tualatin) and Pentium M (Banias/Dothan).  These use the same physical socket on a motherboard, but the keying pins are different on the CPUs themselves.  These are all mobile designs which lend themselves well to VIAs low power designs.  VIA did also make several reference boards for these CPU’s so its clear that there was plans for releasing them to the broader market, and likely with additional motherboard support.

C5J (Left) and C5R (Right) – C5R is a 110nm part with a slightly larger die the the C5J

Another socket was just being developed at the time of this agreement, and that is perhaps the most interesting.  Intel LGA775 chips began sampling in late 2003, which is after the grace period of 3 years had begun so it would make sense for VIA to not develop CPU’s using a socket they were going to lose access to in a few years.  The package likely was in development for a couple years prior which is likely why VIA made a few (likely VERY few) samples for it.  The samples are marked C5R which is a C7 Esther core, if VIA’s naming is consistent, this would be the TSMC 110nm version of the 90nm C5J.

C5R With heatspreader and with heatspreader removed.

The Esther core code names are a bit confusing because of how some CPUID programs identify them. X-86-guide.net has a quite nice ID guide that goes into some great detail on them.  In summary there was a 90nm Rev A C5J made by IBM, and later a 90nm C5J (called Rev D) made by Fujitsu with some additional features.  This Rev D part often gets identified as a C5R, or a C5J shrink, neither of which is correct.  The actual C5R (and related C5Q) were what appear to be backup plans for the IBM produced parts, using a larger 130/110nm process at TSMC. Looking at the mPGA479 unfinished packages (labeled C5J and C5R) the die attach area on the C5R is actually slightly LARGER then the C5J (~35mm2 compared to 28mm2 of the C5J)

C5R Esther – 110nm TSMC in LGA775

Most VIA samples are labeled with the code name in Cxx format and not the marketing code name (Esther Isaiah etc) as each of the Marketing code names (for lack of a better term) consisted of many actual sub-cores.

Looking at the table above we can see VIA took many roads in the development of their CPUs, with many that went nowhere.  Some may see this as a lack of direction or focus, but in a lot of ways VIA seemed to be trying to figure out the best CPU for the market at the same time they were trying to make the best CPU from an engineering standpoint.  Where these two paths converged you had a marketable CPU that made it into mass production, and where they didn’t, or where legal road blocks arose, the design was canceled.  VIA’s CPU development is even more obscure now, though they have made a few other designs we will cover in a later article, as well as the return of Intel to the VIA party.

This is turning into a bit of a series on Soviet processors.  Continuing from our article earlier on the 1801VM2 LSI-11.  The 1801VM3 is the further development of 1801VM1/VM2 and is the highest performance microprocessor in 1801 series. It’s a 16-bit single-chip microprocessor that includes an operating unit, a firmware control unit, an interrupt unit, a memory controller and Q-BUS control unit. A distinctive feature of 1801VM3 is a large amount of addressable memory (4MB vs 64K for the 1801VM1 and 64k+64K for the VM2), high performance and ability to connect a floating-point coprocessor 1801VM4.

1801VM2 die

1801VM3 Die

1801VM3 Specifications

• Number of processor Instruction: 72 Fixed Point and 46 Floating Point (with 1801VM4 FPU)
• Address Space: 4MB
• General Purpose Registers: 8
• Manufacturing process: 4 micron N-channel silicon gate MOS technology (later migrated to 3 micron)
• Die size 6.65 × 8 mm
• Transistor count: 28,900 active transistors, 200,000 integral elements
• Clock rate: 4MHz  (1801VM3V) 5MHz (1801VM3B) 6MHz (1801VM3A, upgraded to 8 in 1991)
• Performance: For register based operations (like addition) up to 1,500,000 instruction/s (1.5 MIPS)
• IRQ Lines: 4
• Supply voltage + 4.75V-5.52V
• Power consumption: 1.7-2 W
• Packages: CDIP64 (KM1801VM3) LQFP64 (KA1801VM3) CQFP64 (KN1801VM3/N1801VM3)

Like the VM2 before it the speeds were denoted by a series of dots on the package (or lack thereof)

KM1801VM3A – 6MHz (no extra dot) CDIP64 package from 9008

KM1801VM3B – 5MHz (one extra dot) CDIP64 package from 9003

KM1801VM3V – 4MHz (two extra dots) CDIP64 package from 9202

KA1801VM3 – 8MHz (no extra dot – post 1991) PQFP64 package from 9108

N1801VM3 – 8MHz (no extra dot – post 1991) CQFP64 package from 9324 – Remarked from a military part (rhombus marking marked over)

The KM1801VM3 appeared as part of the DVK line of computers, starting with the DVK-3M model (PCB ”Electronics МС 1201.03” and “Electronics МС 1201.04”).  Using the same ISA (Instruction Set Architecture) allowed DVK (and others) to rapidly update their computer line when new processors were available, and allow for a wider software base.  This is very much like the original IBM PC using the x86 architecture.  The transition from 8086 to 80286 was relatively easy to design, and nearly seamless for the end user.

DVK PCB Electronics МС 1201.03 board on the top.

Many devices built on the basis of the 1801 series CPU contain other microcircuits of the same series (support circuits).
In addition to microprocessors, this series includes:
– ULA 1801VP1-xxx
– masked ROM 1801REх-xxx
– EEPROM 1801RR1

ULA and EEPROM

The 1801VP1-xxx is a ULA- (Uncommitted Logic Arrays). It’s made using a 3 micron N-channel silicon gate MOS technology with one metal layer. First, base silicon wafers are made that contain transistors. These are doped regions of silicon and a separate oxide-insulated layer of polysilicon gates. Then all this is covered with an oxide layer. Base wafers are ready.

In this form, the wafers can be stored for a long time or transferred to another fab. All 1801VP1-xxx chips, regardless of number, have the same structure and arrangement of transistors. And they are made on the same base wafers.

KR1801VP1-22 die

Differences between the chips appear only at the last stage of manufacturing. In the upper oxide layer, the die is etched by photolithography to access the required transistors. And then form a metallic pattern from aluminum. This pattern defines the electrical circuit. The number in the marking identifies the purpose of the chip. For example, 1801VP1-033 is an external device controller.  This is similar to how a MaskROM is made but instead of only memory elements, it contains logic elements allowing for a custom IC to be made (like a mask programmable PAL/GAL)

KR1801VP1-119

The 1801VP1-119 is a companion chip for 1801VM3. It can be said to be the “north bridge“.
The 1801VP1-119 performs the following functions:
-forms control signals for DRAM;
-forms control signals for system SRAM;
-generates signals to select system ROM;
-generates control signals for detection and correction of memory errors (EDC) using Hamming code (555VGH1). Error correction circuits reduced performance by 10-15%. Therefore in some computers, there were jumpers to enable/disable the EDC
-buffer data register control;
-generate other signals

This was the beginning of what would be come chipsets, replacing loads of TTL with custom circuits.  The exact same evolution was occurring in the west with the PC environment, until nearly all the support circuits were integrated into just a couple large ASICs.   Its interesting to see the development paths of the Soviet computers and the West.  While they were entirely different instruction sets, they evolved in very much the same way.  East or West, LSI-11 or x86, at the end of the day, a computer is a computer and will evolve in similar fashion.

The Soviet-made 1801VM2 CPU (a binary-compatible implementation of the PDP11 instruction set and QBUS interface) was developed in 1982. The 1801VM2 is a further development of the earlier 1801VM1 doubling the original 5MHz clock speed. From a constructive standpoint this CPU is a completely independent development.

1801VM2 die – 1983 dated

1801VM2 Specifications

• Number of processor Instruction: 72
• Manufacturing process: 4 micron N-channel silicon gate MOS technology
• Die size 5.3 × 5.35 mm
• Transistor count: 18,500 active transistors, 120,000 integral elements
• Clock rate: Up to 10 MHz
• Performance: For register based operations (like addition) up to 1,000,000 instruction/s (1 MIPS) – for operations like multiplication, up to 100,000 instructions/s
• Supply voltage + 5V
• Power consumption: up to 1.7 W
• The case is 40-lead, ceramic DIP (KM1801VM2) or plastic DIP (KR1801VM2). (a surface mount version was also made)

To increase noise immunity in comparison with 1801VM1, additional ground contacts were made for the address / data bus.
The 1801VM2 was manufactured at two factories: Angstrem and Solnechnogorsk Electromechanical Plant (SEMZ).  As was typical of the time speed grading was done by adding extra marking to the chips post-testing.  Its very easy to miss these, if a chip was tested at 10MHz and passed it received no extra marking and was considered an 1801VM’A.’  If the device failed at 10MHz but ran at 8MHz a small dot was added to the package (and was considered a grade ‘B’ device).  This dot was not to be confused with the dot for the pin one marker, though often placed…next to it.

Ceramic DIP 1801VM2A Angstrem – 1989 No extra dot

Ceramic DIP 1801VM2B Angstrem – 1987 – Note the extra dot in this case by the date code

Plastic DIP 1801VM2A Angstrem – 1990

KN1801VM2- Angstrem 1985 CQFP Surface mount version (image Baator)

Ceramic DIP 1801VM2 Solnechnogorsk Electromechanical Plant – 1990 – Extra dot by pin 1 marker

In comparison with 1801VM1, expanded arithmetic instructions (MUL, DIV, ASH, ASHC – part of a the set of PDP-11 EIS), and also operations from the floating point instruction set (FIS) were added. The FIS instructions (FADD, FSUB, FMUL, FDIV) are realized through subroutines – when performing these instructions there is a special type of interrupt and the program handler in memory (“shadow” system ROM K1801RE2) of the console mode is executed, a ‘firmware’ style of FIS implementation, as its not truly hardware (the ROMs break down the FIS instructions into something the 1801VM2 can execute)
During the design of the microprocessor, a microcode error was made, leading to a malfunction of the processor when reading with addressing method 17 ( MOV (PC), R0).

DVK-1 Computer

The 1801VM2 was the heart of a number models of DVK computer. DVK was developed at the Research Institute of Precision Technology , Zelenograd (just outside of Moscow). The first model DVK-1 was developed in 1981, and released in 1983. Architecturally DVK copies mini-computers from DEC PDC-11 and PDP-11. By 1990, 200,000 DVK computers of the nine different models were produced.

Romashka Word Processor

Use of the processor continued well into the 1990’s. The “Romashka” belonged to the latest generation of electronic typewriters, which in their functionality were close to computer text editors. This typewriter made it possible to automatically format text (set alignment, change the spacing between characters and between lines, use bold and underlined fonts, etc.) and had an electronic memory of at least one page (3800 bytes).  In the West these half typewriter half computer were called Word Processors, and were quite popular through the 1980’s.   The machine’s control unit was a microcomputer based on the KM1801VM2 processor.
“Romashka” was produced by the Kursk PO “Schetmash” in the first half of the 1990s.

“Electronics IM-05 “- Soviet chess computer, contains 1801VM2 inside. It was a continuation of the line of chess computers “Electronics”. Produced by the Svetlana Association, Leningrad.

In 1984, the military-grade microprocessor 1806VM2 was released.
This microprocessor functionally corresponds to the 1801VM2, but is made using CMOS technology.

• Clock rate: up to 5 MHz
• Number of Instructions: 77
• Contains 134,636 integral elements
• Power consumption: up to 0.025W

The 1806VM2 developers fixed the microcode bug present in 1801VM2 (much to the relief, or annoyance of programmers). The 1806VM2 was supplied in a 42-lead dual in-line ceramic package with flat leads, N1806VM2 in a 64-lead CQFP. The rhombus marking on the chips denotes a military-grade device.

1806VM2 – Angstrem 1991 in the nice pink flat pack

N1806VM2 – Angstrem 1999 in a Ceramic quad flat pack

CQFP N1806BM2 on a ceramic substrate forming a military Single Board Computer – circa 1987 (image Baator)

These 1806VM2 are still being made by Angstrem, if you need to build a PDP-11 computer to run Tetris on, or repair a Buran shuttle you may have laying around.

In 1990, a radiation-hardened microprocessor was introduced, compatible with the 1806VM2, known as the 1836VM2/N1836VM2.  Just like in other countries, existing code base and known reliability are more of a driver of what the military/industry uses than having the latest and greatest.  There are still MIL-STD-1750A processors being made and used, rad-hard 8051s and 80186s, and Soviet PDP-11 processors right there with them.

Photos of microprocessors from the collection of Perfiliev Andrey (Andreycpu).
Article written originally by Contributing Author Vladimir Yakovlev (edited by cpushack)

IBM 4020 Q-Pacs – 1960’s

Back in the late 1950’s two things were happening (ok more then 2 but 2 relevant to todays discussion) the military was looking to replace the new but now already out of date tube based SAGE and AN/FSQ-7 Strategic Air Command (SAC) computers, and multiple bits of data were beginning to be called bytes.  The SAC was in charge of all of the US’s Strategic bombers, ICBMs, and detecting/tracking the threats of bombers/ICBMs from the USSR.  The older tube based SAGE computer was designed for relaying, consolidating, and displaying data from Early Warning RADARs across North America to paint a situation picture of what was going on.  It worked fine, for bombers, but the late 1950’s also brought about ICBMs, and ICBMs are much much faster then mere bombers.  The SAGE, and the AN/FSQ-7 lacked the processing speed to keep up with the changing data from a RADAR track of an ICBM so something faster was needed.

Each module weighs around 90 grams

IBM developed and proposed the AN/FSQ-31 (and the FSQ-7A which got renamed the FSQ-32) which were based on the newly developed IBM 4020 military computer.  The IBM 4020 was completely transistor based and designed for reliability and speed.  Marketing materials of the time refer to its ‘resistance to the effects of nuclear blast,’ clearly this was the 1950’s.  At the heart of the 4020 designs was the Q-Pac. These were pluggable, ceramic encapsulated circuit packages. The majority of all logic requirements can be met
by seven basic types of Q-Pacs, each containing from one to four circuits. The use of transistors, diodes, and resistors/caps on each Q-Pac served as what TTL/RTL of the 1960’s/1970’s formed, discrete logic elements, albeit simple ones. In the 4020 the computer was divided into modules (racks) which each contained 16 drawers. Each drawer could hold 96 individual Q-Pac (or 48 double Q-pacs).  That’s 1536 logic elements per module, and the 4020 had 8 modules, resulting in around 12,288 Q-Pacs.  It appears each Q-pac could support 6 discrete transistors, so the 4020’s basic data path (not counting memory, I/O or storage subsystems would max out at 73k transistors.  Obviously there would not be a system that was ALL transistors but this gives us an idea of the scale of the computer. This is around what the Motorola 68000 CPU had or a Intel 80186.  The typical 4020 (again not counting the peripherals) was water cooled, used 13kw of power and took a good 85 sq ft of floor space.

Five simple transistors in the one on the left, and a pair of diodes on the right.

The 4020 was a 48-bit word length (pus 2 parity bits) computer and was capable of around 400,000 Instructions per second with a 2.5microsecond cycle time (6.25MHz).  It supported 128kwords of drum storage (remember 48 bit words, so this is about 6Mbit.  The 4020 also supported byte processing, using the 48-bit word as 8 6-bit sections which IBM called bytes.  This is one of the first official commercial usages of the term ‘byte’ for a chunk of data.  We think of bytes as 8-bits but thats only a standard thats been around the last 30 years or so.  Back in the 1950’s it was the wild west of data naming.  It was common to use 6-bits for BCD (Binary coded Decimal) and 6-bits to represent characters, so a 6-bit byte was only natural for IBM to use.  This eventually gave way to the 8-bit bytes we all know and love by the late 1960’s, though some processors even in the 1970’s used 12-bit words (Intersil 6100 and some PICs) and other oddities (14 bits from the PIC16).

AN/FSQ-31

The process of integrating the 4020’s into SAC facilities took longer then expected, not being completed until 1968, by which time they were of course outdated again.  By 1975 most of them had been replaced by newer Honeywell systems.  Interestingly, the 4020’s tube driven predecessor lasted in some bases until the early 1980’s.

It wouldn’t surprise me if, even after 60+ years, these Q-Pac modules still worked, after all, that was their intended design, to be rugged and reliable.

The Q-Pacs are in a lot of ways an early predecessor the IC’s of today, a single module containing various logic elements, while not on a silicon die, they were ‘built’ by hand, on a ceramic substrate.