January 17th, 2014 ~ by admin

Zilog Packaging Marketing Kit

Zilog Packages available in 1985

Zilog Packages available in 1985

Last week we showed you an educational kit from Zilog showing the process involved in making and assembling a Z80 processor, from polished wafer to packaging.  Zilog also made a kit for marketing the various packages used.  This kit contains a shrink DIP 64 pin socket, a shrink DIP 64pin package, a 48 pin DIP and 40 pin DIP, all the common packages used at the time.

Zilog Packages - Z8 Z80 Z800 and Z8000

Zilog Packages – Z8 Z80 Z800 and Z8000

At the time is a little hard to track down as no date is provided with this kit.  We can get very close though looking at the back where Zilog lists which devices are available in these packages.  The usual Z80 and Z8000 series are both there as well as the Z8 microcontroller family.  The one odd-ball is the Zilog Z800.  The Z800 was an upgraded Z80 released in 1985, adding on chip cache an MMU and a vastly expanded instruction set (over 2000 instruction/addressing modes).  It was wholly unsuccessful partly do to bad marketing by Zilog, and partly because it did more then it needed to. It never entered mass production, and by 1986 Zilog has redesigned it, converted the design to CMOS (from NMOS) and released it as the Z280 which met the same fate as the Z800.  It seemed that making an overly complicated Z80 wasn’t what the market wanted.  THe Z180 (designed by Hitachi) and the Zilog eZ80 (released in 2001), have enjoyed much wider success, mainly because they kept closer to the simplicity of the original Z80.

So when was this kit put together? Likely 1985, as the Z800 was nly talked about for a few months before quietly being put away.

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January 9th, 2014 ~ by admin

Zilog Educational Sample Kit

Zilog Z-80 Kit - Click for full size

Zilog Z-80 Kit – Click for full size

Here is a neat kit from Zilog.  Its an Educational Kit showing some of the steps of producing a Z-80 processor.  It includes:

  • A raw polished wafer slice before any etching has occured.  This is what a processor starts out with (sliced from a single large ingot)
  • A slice of an etched wafer.  In this case it appears to be some sort of memory, but the process is the same for a processor.
  • Several cut die, these are cut from a wafer after testing.  The red dot notes that these particular dice failed one or more of the tested and should be discard.  Thats probably why they made it into this kit rather then a saleable device.
  • An bare unfinished package.  These packages are rarely if ever made by the company making the processor.  They are made by companies such as NGK (who also makes spark plugs) and Kyocera.  The bottom of the die cavity is usually connected to the ground pin of the package.
  • Next is a package with the die placed in the die cavity.  No bonding wires are installed in this example but that would be the next step.  The very fine gold bonding wires connect the pad ring on the edge of the die, to the pads in the die cavity.  Those [ads are connected through the package to the 40 pins of the ceramic DIP package.
  • Finally we have a completed device.  The lid is usually soldered or brazed onto the package and markings applied.  The marking on this example make it a ‘Marketing Sample’ as they are there solely for looks, rather then to identify the device, its date, and lot.

These types of kits were produced for educational use, and given to schools, as well as sales people to assist in marketing Zilog’s various products

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January 6th, 2014 ~ by admin

HP PA-RISC PA-7000 – Multichip RISC

HP 1FZ3-0001 PA7000 66MHz - 1991

HP 1FZ3-0001 PA7000 66MHz – 1991

Welcome to 2014 and a new year of exciting processors and technology finds at the CPU Shack Museum.  We’ll spend the next couple weeks posting some of the more interesting finds of 2013 that didn’t get posted before.

The PA-RISC was HP’s architecture meant to unify all their non x86 processors of the 1980′s.  The project began in the 1980′s and produced over a dozen processors designs, ending with the PA-8900 in 2005, though the Itanium borrows heavily from the PA-RISC line.  HP discontinued support for PA-RISC servers in 2013 and recently announced that they will discontinue use of the Itanium as well.

Early PA-RISC processors were multi-chip designs such as this PA-7000. The PA-7000 pictured is only the CPU, the FPU was a separate chips, as was the L1 caches (no support for L2 caches). A memory controller was also a separate chip.  Made on a 1 micron process the PA-7000 had 580,000 transistors and ran at 66MHz.  Early versions had 2 lugs for the heatsink on the package while later versions had only a single lug.

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November 19th, 2013 ~ by admin

MAVEN To Mars: Another BAE RAD750 CPU

MAVEN to Mars - RAD750 Powered

MAVEN to Mars – RAD750 Powered

NASA has successfully launched the $671 million MAVEN mission to Mars for atmospheric research.  Like the Mars Reconnaissance Orbiter it is based on, it’s main computer is a BAE RAD750,  a radiation hardened PowerPC 750 architecture.  This processor first flew on the Deep Impact Comet chaser and is capable of withstanding up to 1 million rads of radiation.  The entire processor sub-system can handle 200,000 rads.  To put this in perspective, 1000 rads is considered a lethal dose for a typical human.  Likely much higher then a Apple Mac G3 that the PowerPC 750 was originally used in back in 1998 as well.   The processor can be clocked at up to 200MHz though often will run slower for power conservation.

The MAVEN should reach Mars within a few days of the Indian Space Agency’s $71 million Mangalyaan Orbiter launched earlier this month.  MAVEN is taking a faster route, at the expense of a heavier booster and larger fuel consumption.  The Mangalyaan Orbiter’s main processor is the GEC/Plessey (Originally produced by Marconi and now Dynex) MAR31750, a MIL-STD-1750A processor system.

November 17th, 2013 ~ by admin

Itanium is Dead – And other Processor News

Itanium Sales Forecasts vs Reality

Itanium Sales Forecasts vs Reality

‘Itanium is dead’ is a phrase that has been used for over a decade, in fact many claimed that the Itanium experiment was dead before it even launched in 2001.  The last hold-out of the Itanium architecture was HP, likely because the Itanium had a lot in common with its own PA-RISC.  However HP has announced that they will be transitioning their NonStop sever series to x86, presumably the new 15-core Xeons Intel is developing.  Itanium was launched with goal of storming the server market, billed as the next greatest thing, it failed to make the inroads expected, largely due to the 2 decades of x86 code it didnt support, and poor initial compiler support.  Many things were learned from Itanium so though it will become but a footnote, its technology will live on.

Interestingly other architectures that seemed to be n the brink are getting continued support in new chips.  Imagination, known for their graphics IP, purchased MIPS, and now has announced the MIPS Warrior P-class core.  This core supports speeds of over 2GHz, and is the first MIPS core with 128 bit SIMD support.

Broadcom, historically a MIPS powerhouse, has announced a 64-bit ARM server class processor with speeds of up to 3GHz. Perhaps ironic that ARM is now being introduced into a market that Itanium was designed for. Broadcom has an ARM Architecture license, meaning they can roll their own designs that implement the ARM instruction set, similar to Qualcomm and several others.

POWER continues to show its remarkable flexibility.  Used by IBM in larger mainframes in the POWER7 and POWER8 implementations it crunches data at speeds up to 4.4GHz.  On the other end of the spectrum, Freescale (formerly Motorola, one of the developers of the POWER architecture) has announced the 1.8GHz quad-core QorIQ T2080 for control applications such as networking, and other embedded use.  These days the POWER architecture is not often talked about, at least in the embedded market, but it continues to soldier on and be widely used.  LSI has used it in their Fusion-MPT RAID controllers, Xilinx continues to offer it embedded in FPGAs and BAE continues to offer it in the form of the RAD750 for space-based applications.

Perhaps it is this flexibility of use that has continued to allow architectures to be used.  Itanium was very focused, and did its one job very well. Same goes for the Alpha architecture, and the Intel i860, all of which are now discontinued.  ARM, MIPS, POWER, x86 and a host of MCU architectures continue to be used because of their flexibility and large code bases.

So what architecture will be next to fall? And will a truly new architecture be introduced that has the power and flexibility to stick around?

November 1st, 2013 ~ by admin

nCube and the Rise of the HyperCubes

nCube/2 Processor - 20MHz The logo is a tesseract - 4-way Hypercube

nCube/2 Processor – 20MHz
The logo is a Tesseract – a 4-way Hypercube

In 1983 Stephen Colley, Dave Jurasek, John Palmer and 3 others from Intel’s Systems Group left Intel, frustrated by Intel’s seeming reluctance to enter the then emerging parallel computing market.  They founded a company in Beaverton, Oregon known as nCube with the goal of producing MIMD (Multiple Instruction Multiple Data) parallel computers.  In 1985 they released their first computer, known as the nCube/10.  The nCube/10 was built using a custom 32-bit CMOS processor containing 160,000 transistors and running initially at 8MHz (later increased to 10).  IEEE754 64-bit floating point support  (including hardware sqrt) was included on chip.  Each processor was on a module with its own 128KB of ECC DRAM memory (implemented as 6 64k x 4 bit DRAMs.)  A full system, with 1024 processor nodes, had 128MB of usable memory (160MB of  DRAM counting those used for ECC).  From the outset the nCube systems were designed for reliability, with MTBFs of full systems running in the 6 month range, extremely good at the time.

The nCube/10 system was organized in a Hypercube geometry, with the 10 signifying its ability to scale to a 10-way Hypercube, also known as a dekeract.  This architecture allows for any processor to be a maximum of 10-hops from any other processor.  The benefits are greatly reduced latency in cross processor communication.  The downside is that expansion is restricted to powers of 2 (64, 128, 256, 512 etc) making upgrade costs a bit expensive as the size scaled up.  Each processor contained 22 DMA channels, with a pair being reserved for I/O to the host processor and the remaining 20 (10 in + 10 out) used for interprocessor communication.  This focus on a general purpose CPU with built in networking support is very similar to the Inmos Transputer, which at the time, was making similar inroads in the European market.  System management was run by similar nCube processors on Graphics, Disk, and I/O cards.  Programming was via Fortran 77 and later C/C++. At the time it was one of the fastest computers on the planet, even challenging the almighty Cray.  And it was about to get faster.

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October 25th, 2013 ~ by admin

Honeywell 1750A-5V: MIL-STD-1750A Lives On

Honeywell 1750A-5V -2008

Honeywell 1750A-5V -2008

While its not in the best condition I was still pleased when it came in.  MIL-STD-1750A was first developed in 1980 to provide a uniform architecture for military computing, while allowing competition in the market to produce different versions at a hoped for reduced cost.  By 1996 though the 1750A was declared inactive for new designs in the US military.  It had been widely replaced by other more powerful commercial designs, notably the 80386 and 80486.  Many militaries around the world continue to use the 1750A and the US Military continues to need spares.

Honeywell continues to produce the 1750A-5V, a single chip implementation of the 1750A with on-board 40-bit FPU, much like Fairchild’s commercial F9450.  Produced on a CMOS SOI (SIlicon On Insulator) 0.65u process the 1750A-5V runs at up to 40MHz, twice as fast as most did in the 1980′s.  This particular example was produced in 2008 though Honeywell continues to make and advertise the 1750A.

The radiation hardened version was used on the Cassini Orbiter (now orbiting Saturn), ESA’s Rosetta Comet probe as well as the Guidance computer for the Air Force’s Titan 4 missile.

October 8th, 2013 ~ by admin

When a Pentium 166 isn’t a Pentium 166

Pentium 166 Faked from Mobile 120

Pentium 166 SY016 Faked from Mobile 120 SY027

Here is an interesting example of what led Intel (and other manufacturers) to start locking down multipliers on their processors as well as adding anti-counterfeiting measures.  This processor appears to be a 166MHz Pentium Processor, which in 1997 sold for around $200.   A 120MHz Mobile Pentium sold for less than $100.  Thus processors of lower speeds were often remarked by unscrupulous dealers and sold as higher speed parts.   The forgeries had to be made quick, as processor prices dropped very quickly, the 166MHz Pentium debuted at nearly $1000.  Most Pentium fakes were made by painting over the original markings and painting/engraving news ones.  Some of the better fakes ground down the old markings first.  Nearly all are easy to spot by the trained eye, wrong fonts, date mismatches, etc.

This particular example, from somewhere in 1997, was faked from a Pentium 120MHz mobile to a 166MHz desktop Pentium.  As far as fakes go this was a fairly conservative one.  Often 166s were faked from 100s or even 75s.  The 120 was a 2x60MHz processor running at 3.1V, while the 166 is 2.5×66 (you see why locking the multiplier discouraged faking?) running at 3.3V.  This resulted in a 28% overclock at about a 6% voltage increase.  In this case the processor likely ran fairly well, if perhaps a bit warm.  Some of the more extreme fakes resulted in very unstable systems due to overheating and pushing a processor well beyond what it was designed for.

Before removing paint

Before removing paint

Today counterfeit chips are still a major problem, though it was shifted from the consumer market, where prices are generally low, to the military and industrial market, where prices are high, and there is still demand for older devices.

October 6th, 2013 ~ by admin

Decryption by an Intel 80386 – Military Style

Raytheon KGV-25

Raytheon KGV-25 – Click to Enlarge

Sometimes we get processors in on boards that are just too interesting, or too good looking to remove.  That is the case with this KGV-25 correlator board.  It is a processing systems used for decrypting communications that was in wide use by the US (and likely other) militaries in the 1990′s.  The KGV-25 could receive encrypted UHF data at rates of up to 400Mbps as part of the Multi-Mission Advanced Tactical Terminal (MATT). More information on the MATT can be found here on the FAS website.

As is typical of military equipment the system did not use the latest and greatest available at the time (this board is from 1994 so the Pentium era).  The board is run by a time proven and reliable Intel 80386 processor running at 25MHz. In addition to the MQ80386-25/B (MIL-STD-883B spec 386 processor) the board contains:
Intel MQ82380-20/B  - DMA Controller for interfacing with all the assorted SRAM on the board
Intel MQ82592/B – LAN Controller for interfacing with the rest of the system
VLSI VM05403 USART – Universal Asynch/Synch Receiver Transmitter
and on the back is a MQ80387-25/B Math-coprocessor for the 386 and 4MB of 35ns SRAM

Raytheon KGV-25 - Back

Essentially a complete 80386 system, of similar performance to a higher end system int he late 1980′s.  Just with a lot more gold, and built to take a lot more abuse then your average beige box of the 80′s

 

 

September 28th, 2013 ~ by admin

Realtek RTL8186: MIPS by Lexra

Realtek RTL8186 Lexra LX5280 MIPS with DSP Extentions - 2006

Realtek RTL8186 Lexra LX5280 MIPS with DSP Extensions – 2006

The MIPS architecture was created in 1985 from a project at Stanford University.  It was one of the first licenseable architectures.  A company could buy a license and make their own MIPS architecture processors.  By the 1990′s this had become fairly common and many companies were making MIPS processors, including Performance Semiconductor, IDT, NEC, Toshiba, LSI and more.  In 1992 MIPS Computer Systems, Inc. was bought by SGI, in order to guarantee a supply a continued development of new MIPS designs for SGIs computers.  It did continue to license the design to other companies as well, fostering competition which helped lower prices for SGI.  In 1998 SGI spun off MIPS into its own company once again, as SGI at the time had decided to move towards Intel’s Itanium architecture (this should sound familiar, DEC and the Alpha suffered the same fate).  By 2008 MIPS was losing money and in 2013 what little remained (having used most of their cash to buy, and then sell at a loss Chipidea) of them was bought by Imagination Technologies (makers of the PowerVR line of graphic solutions, used notably in the Apple iPhone’s A4, A5, A6, and likely A7 processors).  But there is a bit more to the story of MIPS, a seemingly small chapter that very well could have changed history and certainly changed the success of MIPS.

In 1997 a small company called Lexra was started. Lexra was a semiconductor Intellectual Property company.  They designed processors and licensed the designs.  What made Lexra different is that they designed and licensed soft-cores.  A soft core is an RTL (Register Transfer Level) model of the processor.  It is usually written and delivered in an HDL (Hardware Descriptive Language) such as Verilog or VHDL and the purchaser may compile it down to whatever actual transistor level hardware they like.  This is exactly how ARM works today, but in 1997 ARM only licensed hard cores, cores already compiled down to the gate level and ready for implementation on a given fab process technology.  This allowed them to have tighter control over the design and its performance, but made integration much harder into other products.  A soft core like Lexra designed enabled rapid integration into a variety of SoCs and other applications.  Lexra’s chosen architecture was MIPS and that is where the story gets interesting.

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