Zycad IU – Interface Control Processor for the XP series of Emulators. Fab’d by LSI in 1990

Zycad was founded in 1981 to develop and market simulation acceleration technology.  This was to allow new chip designs to be tested/simulated before being laid out in silicon, providing the possibility to catch faults earlier in the design process.  The earlier faults can be caught, the easier, and less expensive they are to fix.

By the late 1980’s Zycad a leader in simulation tech and set the standard for simulation systems.  They provided the simulation software environment, a simulation/hardware descriptive language (Zycad Intermediate Format), as well as custom hardware accelerators for the logic/fault simulation.

In 1987 Zycad shipped a customized system to LSI, which LSI was then able to use, and market for all their customer designs, notable the LSI version of the SPARC processor.  This close relationship with LSI also benefited Zycad, as it was LSI who fab’d Zycad’s custom silicon, the heart of their emulation system. In the late 80’s and early 90’s the main Zycad emulation system was the XP series.  The XP series (consisting of the 100, 140 and 200) was based on 2 main IC’s.  The Interface Control Processor (IU) was the interface between the host processor (either a SPARC system, or a VAX type workstation) and the Logic/Fault Emulation Processors (PU’s).  One IU could control multiple PU’s and a typical system (such as the XP-140) had 1 IU and 5 PU’s.  These systems could emulate from 256,000 (XP-100) to 4 million (XP-200) gates at speeds from 2.5 millions events/sec to 40 million events/sec.

Zycad XP-140 system board with 1x IU and 5x PU Emulation processors

In 1996 Zycad announced the Lightspeed simulation server, massively parallel simulation server running on from 64-4096 processors, each with their own on chip memory.  These were implemented on 0.5u ASICs from LSI.  This technology was sold later that year to one of Zycad’s competitors, IKOS, leaving Zycad to enter the field of FPGAs as Gatefield, which later would be bought out by Actel.  IKOS was later acquired by Mentor Graphics, a company that worked extensively with Zycad and their emulators in the 1980’s and 1990’s.  The customer, had now become the owner.

What Zycad began in the 1980’s continues today on a massive scale.  The XP series and the later Lightspeed simulation server are in many ways similar to the Palladium and Palladium II processors by Quickturn/Cadence that we discussed lat year.

Hardware simulation is a field that continues to grow in scale and complexity.  As systems become more and more complex, transistors counts continue to rise, and the need to make sure it works, before putting it in silicon remains.

Teranex Piranha TN3260B – 1024 PE Array @ 64-90MHz

The GAPP (Geometric Arithmetic Parallel Processor) was designed in 1981 at Martin Marietta, which later became Lockheed Martin Electronics & Missiles.  It was funding in large part by the US Dept. of Defense as a way to develop technologies for ultra high-speed image processing.  There was a strong need for image processing, in near real time for military applications, in particular pattern recognition.  Being able to process a moving image and match its features to known patterns was very useful for targeting of many weapons system.

The GAPP processor was a massively parallel SIMD (Single Instruction Multiple Data) processor.  SIMD works very well on large sets of data that are processed in the same way.  In the design of GAPP, this data set was the 2D-array of an image, or frame, from a video.  The GAPP is at its core a very large array of simple processors, called processor elements (PE).  Each PE is relatively simple, containing a single bit ALU and registers/memory.  Each PE handles a single pixel of the image/frame, and is connected in a 2-D mesh to its 4 nearest neighbors.  This allows arrays of these PE’s to scale very well.  By 1992 Lockheed had GAPP systems with 82,944 elements and by the 2000’s systems were available with nearly 300,000.

In 1998 TeraNex was formed to commercialize this technology, and in 1998 there was a looming problem in television, one that the GAPP, and newly formed TeraNex were well suited to solve.

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6801/6803 Expansion Board and PCP

After several months of development an expansion for the 680x/650x Test system is now available to support the very popular and widely used 6801 and 6803 MCUs.  The Motorola 6801 was one of the first (with the 6802) MCU’s that Motorola made based on the MC6800 8-bit processor.  It includes RAM/ROM, Serial I/O and timers.  The test board tests the function of the base CPU, the timers/data capture, and the Serial I/O.  The MC6803 is a 6801 without the built-in ROM and with less I/O.

The expansion supports both types as well as their copies/derivatives made by Hitachi, Fujitsu, SGS and others.  The expansion is included in the complete 680x/650x Test system, bringing its total supported processors to well over 35.  The expansion does require updated firmware, which is included in all new systems (and available to upgrade previously sold systems.)

Intel D80130-3 OSP – Engineering Sample – Early 1982

A seemingly impossible occurrence today, but something that Intel has faced in the past.  It is common for customers to need chips that are no longer in production, either for repair of legacy systems, or to keep an old but reliable design in production.  Typically these parts can be sourced on the secondary market, or from End-of-Life suppliers such as REI, or InnovASIC.  But what happens when Intel themselves needs a chip that they previously made, but no longer do?

Such was the case with the 80130 Operating System Processor.  The 80130 was a co-processor designed in 1981, to make use of Intel’s high-density ROM capabilities.  The 80130 contained 16K of ROM, 3 timers (compatible with 8254), an interrupt controller (similar to the 8259), and a baud-rate generator.  It was capable of bus management and control and could directly control an 8087 FPU as well.  These are designed to work with the 8086/88 and 80186/188 processors.  The 16K of ROM was coded with 35 Operating System primitives (a subset actually of the Intel iRMX86 RTOS (Real Time Operating System).  This firmware allowed easier support for the constructs typically used in a multitasking OS.  Essentially the 80130 extended the instruction set of the x86 to include higher level OS functions.

Intel D80130-2 – 1983 – Production version (though datasheets continued to be marked ‘Preliminary’ though its entire life)

The original version, called (for no known reason) the 80130-3 was released in engineering sample versions only.  It could run at up to 8MHz allowing it to work with any of the x86 processors of the time.  After some small timing adjustments, the 80130 was released to production as the 80130-2, still keeping with the 8MHz max.  Later references show a 80130 at 5MHz as well as the 8MHz -2 part.  However, the 5MHz part has not been seen (as of this writing) and is likely to exist only in datasheets.

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Aeroflex 5962F0252301VXA = UT80CRH196KDS
F = 3×10⁵ Rad
01 = Mil Temp (-55C-125C)
V = Class V

The MCS-196 is the second generation of Intel’s MCS-96 family of 16-bit processors.  These are a control oriented processor originally developed between Ford Electronics, and Intel in 1980 as the 8060/8061 and used for over a decade in Ford engine computers.  They include such things as timers, ADC’s, high-speed I/O and PWM outputs.  This makes them well suited for forming the basis of applications requiring control of mechanical components (such as Motors, servos, etc).  The 196KD is a 20MHz CMOS device with 1000 bytes of on die scratch pad SRAM. The UT80CRH196KDS (unqualified/not tested for radiation) is priced at $1895.00 in quantities of 5,000-10,000 pieces (in 2002). Fully qualified ones will of course cost a lot more. The KDS is a drop in replacement for the previous KD version, which only supported doses of 100krads.

This obviously lends itself to automotive applications, hard disk control, printers, and industrial applications.  There is however, another application they have found wide spread use in, spacecraft.  Spacecraft are not all to different from a car in the amount of mechanical systems that must be interfaced to the computer controls.  The difference however, is that unlike your car, spacecraft electronics must work, always.  If a car fails, its an annoyance, if a spacecraft fails, it has the potential to cost millions of dollars, not to mention the loss of a mission.  If that spacecraft happens to be the launch vehicle, a failure can directly result in a loss of life.

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Milandr K1986VE91T – 80MHz ARM Cortex-M3

In the early 1990’s a Milandr was formed in Zelenograd, Russia (just a short distance to the NW of Moscow), the silicon valley of Russia, home to the Angstrem, and Micron IC design houses. They are a fabless company, though with their own packaging/test facilities, specializing in high reliability metal/ceramic packages. Most of their products are fab’d in Germany, by X-Fab.  X-Fab was formed in part, from the remains of the Soviet/E. German era VEB Mikroelektronik Karl Marx, in Erfurt Germany, also known as FWE/MME and later Thesys.  In Soviet times it wasn’t uncommon for Soviet companies to use dies produced by FWE in their own packages, so this bit of legacy continues today.

The K1986VE91T is one of Milandr’s top end products, it is an 80MHz ARM Cortex-M3 based processor, and likely one of the largest, if not the largest, Cortex-M3 made.  It is made on a 180nm process and includes 32K RAM, 128K FlashROM, 96 USER I/O, USB, 2 UART and 12-bit DAC/ADC.  Judging by the die, the processor was built with standard licensed blocks, very common for such designs.  Milandr licensed the ARM Cortex-M3 itself in December of 2008, for use mainly in automotive and industrial applications. Milandr is also the very first Russian company to license and use an ARM core.

Analog Devices ADUCM322BBCZ ARM Cortex-M3 80MHz – Same basic core, but in a very much less appealing package

The package, however, is completely unique.  It is a 132 pin CQFP package. There are 33 gold leads on each side of the white ceramic package.  Each row is actually 2 staggered rows, the offset allows the finer lead pitch, and still room to bond the leads to the top of the package.  Soviet processors were often delivered in the most stunning of packages and 25 years later, Milandr keeps that tradition alive.

Each of these processors came with a brief datasheet, complete with inspection stamps for the processor. It is all in Russian, but check it out here.

Milandr made several variations of the Cortex-M3, including the VE92 and VE93 which are internally identical, but with much less I/O available owing to there smaller 64 pin and 48 pin packages respectively. Milandr also made a copy of the PIC17 processor that we covered last year.

A version of the K1986VExx continues to be made by Milandr, but renamed to the MDR32F9Qx.  It continues to have the same basic core, but in a 144 pin package, allowing even greater I/O support.

Matrox SX-900: Serial# 266 – Nov 1984

In today’s age of GPU’s the GPU is often used to offload the x86 processor.  Many tasks are well suited for the thousands of GPU cores on modern graphics cards, tasks that would be a large burden on an x86 processor.  In 1984 though, Matrox took a different approach to high-end GPU design.  Matrox was founded in Canada in 1976, and has been making graphics cards since they first released the S-100 bus ALT-256 in 1978.  Matrox kept up with the hardware changes of the time, released MULTIBUS boards, Q-Bus boards, and eventually PC compatible cards.

The SX-900 was the value (around $2000) version of their 2 board GXB-1000 (that was $3000-4000).  The Matrox SX-900 was a standard MULTIBUS card with support for 640x480x8bit graphics.  It supported a fill rate of 20 MPixels/sec which was very impressive in 1984.  By comparison, the Nvidia NV1 (STG-2000) released in 1995, was only capable of a 12MPixel/sec fill rate, albeit at a richer color depth.  So how did Matrox, in 1984, achieve such performance?

Matrox SX-900: Powered by a 80286-4 Processor and upD7220 Graphics Primitives Processor

Matrox used an Intel 80286 processor, running at 4MHz (the slowest 286 made) as a Display List Processor.  It handles all high level commands (256+) and then controls the rest of the cards hardware, including the NEC uPD7220 Graphics primitive processor and a advanced pixel processor (implemented in PALs/TTL).  Together they bring rather impressive performance.  The board supports up to 4096 colors (in a Lookup Table) but can only display 16 at a time. Interestingly the board has 512K of 150ns DRAM for use as video memory, more than enough for 640×480 graphics.  Also included is 640 bytes of 25ns ECL SRAM (5x AM9122-25PC), and 16K of 120ns CMOS SRAM implemented with 2 HM6264s.  Firmware (the same firmware used for the GXB-1000) is held in 4 27128 EPROMs for simple updating as needed.

The SX-900 was used in CAD systems, industrial automation, processor control, and other applications where data needed to be shown the user graphically, rather then on a green glowing monochrome text display.  One of the more famous applications was the University of Milan (in Italy) where the SX-900 (supported by Intel iSBC286 computing boards) controlled the K800 Superconducting Cyclotron, a 100MeV particle accelerator.  THis cyclotron ended up being moved and completed at Catania, also in Italy.

Many of these boards are still in use, dutifully displaying graphics and providing user interfaces to thousands of processor control systems in factories and institutions around the world.

Stratus XA/R (courtesy of the Computer History Museum)

Making the rounds this week is the Computer World story of a Stratus Tech. computer at a parts manufacturer in Michigan.  This computer has not had an unscheduled outage in 24-years, which seems rather impressive.  Originally installed in 1993 it has served well.  In 2010 it was awarded for being the longest serving Stratus computer, then being 17 years.  Phil Hogan, who originally installed the computer in 1993, and continues to maintain it to this day said in 2010  “Around Y2K, we thought it might be time to update the hardware, but we just didn’t get around to it”  In other words, if it’s not broke, don’t fix it.

Stratus computers are designed very similar to those used in space.  The two main difference are: 1) No need for radiation tolerant designs, let’s face it, if radiation tolerance becomes an issue in Michigan, there are things of greater importance than the server crashing and 2) hot swappable components.  Nearly everything on a Stratus is hot-swappable.  Straus servers of this type are based on an architecture they refer to as pair and spare.  Each logical processor is actually made from 4 physical CPU’s.  They are arranged in 2 sets of pairs.

Stratus G860 (XA/R) board diagram. Each board has 2 voting i860. (the pair) and each system has 2 boards (the spare).  The XP based systems were similar but had more cache and supported more CPUs.

Each pair executes the exact same code in lock-step.  CPU check logic checks the results from each, and if there is a discrepancy, if one CPU comes up with a different result than the other, the system immediately disables that pair and uses the remaining pair.  Since both pairs are working at the same time there is no fail-over time delay, it’s seamless and instant.  The technician can then pull the mis-behaving processor rack out and replace it, while the system is running.  Memory, power supplies, etc all work in similar fashion.

These systems typically are used in areas where downtime is absolutely unacceptable, banking, credit card processing, and other operations are typical.  The exact server in this case is a Stratus XA/R 10.  This was Stratus’s gap filler.  Since their creation in the early 1980’s their servers had been based on Motorola 68k processors, but in the late 1980’s they decided to move to a RISC architecture and chose HP’s PA-RISC.  There was a small problem with this, it wasn’t ready, so Stratus developed the XA line to fill in the several years gap it would take. The first XA/R systems became available in early 1991 and cost from $145,000 to over $1 million.

Intel A80860XR-33 – 33MHz as used in the XA/R systems. Could be upgraded to an XP.

The XA is based on another RISC processor, the Intel i860XR/XP.  Initial systems were based on 32MHz i860XR processors.  The 860XR has 4K of I-cache and 8K of D-cache and typically ran at 33MHz.  Stratus speed rating may be based on the effective speed after the CPU check logic is applied or they have downclocked it slightly for reliability. XA/R systems were based on the second generation i860XP.  The 860XP ran at 48MHz and had increased cache size (16K/16K) and had some other enhancements as well.  These servers continued to be made until the Continuum Product Line (Using Hewlett Packard “PA-RISC” architecture) was released in March of 1995.

This type of redundancy is largely a thing of the past, at least for commercial systems.  The use of the cloud for server farms made of hundreds, thousands, and often more computers that are transparent to the user has achieved much the same goal, providing one’s connection to the cloud is also redundant.  Mainframes  and supercomputers are designed for fault tolerance, but most of it is now handled in software, rather than pure hardware.

HP 12152-60002 A700 Phoenix Processor – 4x AMD AM2903 (1820-2377)

The Lighting processors of the HP A600 and A600+ were good performing for 1982.  They filled the entry and mid range slots of the HP 1000 A Series quite well.  The additional floating point support of the A600+ in 1984 helped considerably as well, but what was needed for truly better performance on the high end was hardware math support.  While the HP A600 took only 9 months to design and release, the A700, released at the same time, took somewhat longer.  The A600 was based on the AMD 2901, which had been released way back in 1975.  The A700 Phoenix was based on its successor, the AM2903.  The 2903 added a few important features to the bit-slicer.  Hardware multiply and divide support,support for more registers, and easier ways to access them, and parity generation.  This is why the A700 took longer to design, the A600 design was begun half way through the A700 to fill the lower end, where the features of the 2903 wouldn’t be as missed.

The A700 performs at the same 1 MIPS as the A600 but supports 205 standard instructions (compared to 182 for the A600 and 239 for the A600+).  It adds more register reference instructions, dynamic  mapping, I/O and more math based instructions.  Cycle time is actually slightly slower, 250ns compared to 227ns for the A600 but the 2903 allows more efficiency making up for the difference.  A typical FMP instruction take 13.75-25.25 microseconds compared to 16.6-26.6 on the 2901 powered A600.  This is a direct result of the hardware multiply hardware included in the 2903.  The A600+, with its faster 2901C’s completes the same instruction in 17-21.1 microseconds, FASTER then the A700. But the A700 has a trick up its sleeve….

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HP A600+ Processor Board. 4x AMD AM2901CDC (1820-3117) 1x AMD AM2904DC and 1x AMD AM2910 (1820-2378). Some versions used 2901’s from National Semiconductor.

In the early 1960’s HP was exploring connecting computers to its various instruments, for control, monitoring, and logging.  The DEC PDP-8 had come out in 1965 as perhaps the first mini-computer and could be used to control HP’s instrument’s.  However, HP determined that it would actually be easier, and faster to design and build their own computers rather than work with DEC.  DEC probably didn’t see HP’s interest as important enough to make it easy (some interfacing for I/O etc would have to be done).  It worked out well for HP however, as this pushed them into an entirely new, and emerging market.

In 1966 HP released the 16-bit HP 2100 (later to be renamed the HP 1000 series).  It was a design that had begun under Union Carbide’s Data Systems Inc, a company HP had recently acquired.  This gave HP a head start, and allowed them to evolve the design to meet their needs (at the time mostly to control instruments).  When released it included not only the hardware but a completely function software suite as well, including a FORTRAN compiler.  They initially ran with a 10MHz clock and a 1.6usec memory cycle time.

Throughout the 1970’s the design evolved, and would lead to many computers.  The 98xx desktop systems using HP’s NMOS BPC Hybrid processor were based on the HP 1000 series.  The design was a fairly simple accumulator based architecture with 2 16-bit accumulators (A and B) and a 15-bit PC and 68-base instructions.  The first version was directly programmed but all subsequent versions were microprogrammed, making alterations and additions to the instruction set much easier, a feature that became important in keeping the HP 1000 around.

The A series were the HP 1000’s of the 1980’s.  Development began around 1980 and the first computers, the A600 and A700, were released in 1982.  These were some of the first LSI based processors for the line.  THe A600 processor was called the ‘Lightning.’  The name “Lightning” came from the Mark Twain quote “Thunder is good, thunder is great, but it is lightning that does all the work.” “Thunder” was a reference to the PDP 11/23, one of DEC’s newer machines at the time.  HP had went from considering using DEC’s computers to run instruments, to the 4th largest maker of such computers in only a decade.  Certainly a fact not lost on either company.

The A600 is an interesting design, it is of course microprogrammed, and is based on AMD AM2901B bit-slice processors, supported by a 2910 microsequencer, and the 2904 status/shift control unit.  The rest of the board is Schottky TTL, PALs, FPLAs. and ROMs.  Each HP 1000 instruction is microcoded into a 56-bit instruction for controlling the 2901’s 2904 and 2910.  These 56-bit instructions directly operation on the processor.  Certain bits interface with certain parts of each chip, so they are directly executed.

A600 – 56-bit microinstruction word directly operates on the hardware (click for LARGE version)

A series of PAL’s contain the microcoding, allowing for easy updating (at the time).  A standard A600 executed 182 standard HP 1000 instructions.  It could do so at a rate of 1 MIPS, with a cycle time of 227 nanoseconds.

Each 2901 is a 4-bit slice processor, and contains 4-bit registers and ALU’s.  The HP 1000 A and B registers are mapped directly to the R0 and R1 registers of the 2901’s and the Program counter resides in R15.  The PAL’s determine what HP 1000 instruction is being executed, and decode it into the proper 2901 assembly code, building the 56-bit instruction word.  This is one of the best examples of how the AMD 2901 (and other bit slicers) were designed to be used.  The end user has no idea, or need to know what is executing their HP 1000 code.  Its is decoded and send to the bit slicers for processing which then return the results to the proper place.  If new functions are needed a new processor does not need to be designed, simply add additional PAL code to decode the new instructions.  And that is exactly what HP did….

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