July 23rd, 2018 ~ by admin

A Sampling of Sample Processors

AMD K6-2 Marketing Sample

During the development of most any given processor many chips are produced before it is released for commercial use.  These pre-production chips serve a wide variety of purposes in the design and debugging of the processor to ensure that the final CPU work well, sells well, and is compatible with all the vendors parts (motherboards, cooling solutions, power supplies, etc).  These chips are generally referred to as samples, and there is several types of them.  We’ll use Intel/AMD as the main examples but most all processor companies work in similar ways.

When a processor design is first being developed, the package for it is also often being developed as well, what will the new processors silicon die reside in?  How many pins? How will it dissipate heat?  This type of testing is often handled with Mechanical Samples.  Mechanical Samples are exactly as they sound, they test the mechanical aspects of the processor, the physical fit of it.  THese are often sent to board/socket manufacturers to ensure the processor will fit in sockets/boards, and with the automated equipment used to build systems.  Cooling solution companies may also receive these to test how a heatsink fits on the CPU. Mechanical samples may not contain a die at all, or may be chips that were tested as bad, or simply just untested chips (Intel used a lot of untested Mechanical Samples in their educational kits).

Thermal Sample for the LGA2011 Sandy Bridge Xeon

The next samples typically made are Electrical/Thermal Samples.  These again do not have an actually processor die in them, but electrically do work.  Electrical/Thermal samples are used to test the power draw and heat dissipation of a processor.  They often use a daisy chain transistor design, which serves to draw/dissipate power.  If a processor is expected to dissipate 135W of heat, a Thermal sample can be made to draw/dissipate exactly that.  These can test the the power supplies on motherboards, as well as the heat dissipation abilities of cooling solutions.  Some Thermal Samples have a temperature sensor added directly to the package to help see what temps they achieve.  Electrical Samples and Thermal Samples could also be used as purely Mechanical Samples too, and this is sometimes seen marked on the sample.

The first samples made that actually contain a functioning processor die are Engineering Samples.  Engineering Samples (also known as ES) are the most well known samples.  Overclockers often like to find ES CPUs as they will often allow for easier overclocking due to some not having locked in speed (multiplier locked).  Engineering Sample CPUs themselves come in several types as well.  Usually the first run is known as ES1, these can be thought of as an ‘Alpha’ version.  They are very likely to be buggy, and rarely run at the same speed as a production chip would.  These exist to test the overall processor design, or some subset of it.  Some are made to test just one part of the CPU, for example , the memory controller, or the cache.  Later versions of

Motorola PowerPC 8260 Engineering Sample (note the PPC prefix)

Engineering Samples are often called ‘ES2.’ These processors are getting closer to final production and are a lot less buggy, these would be considered ‘Beta’ Samples.  Most of the time these are quite usable chips, and often are very similar in clock speed/features to a production processor.   Intel denoted these chips with a Q-spec (such as QBGC) rather then production processor having an S-spec (such as SL5G8).  AMD typically uses part numbers starting with ‘1’ for ES1 CPUs and ‘2’ for ES2 CPUs. (such as Opterons 1S160805L4BGC or 2S16….).  Other companies have similar methodologies.  Motorola (Freescale) used the PPC prefix for most ES CPUs and Texas Instruments uses ‘TMP’ (not to be confused with Toshiba who also uses the TMP pre-fix, but for processors in general). Once a company is fairly confident a design is ready for release one final version is made.

These are known as Qualification Samples (QS).  QS processors almost always have a one to one equivalence with a production part, since that is their purpose, to make sure the design is ready for release.  These processors are by far the most widely made chips, as they are shipped by

Alchemy Au1000 MIPS Processor – Qualification Sample

the thousands to vendors, system builders/integrations, and even the media outlets for review.  The hope is that nothing major wrong is found with them, and that any bugs that are found can be dealt with in software or firmware, not requiring an entire silicon fix.  Intel continues to use Q-specs for these as well, leading to some confusion with the previously mentioned ES CPU’s.  AMD usually uses part numbers beginning with ‘Z’ for QS CPU’s and like Intel, does not offer these CPU’s for sale to the general public, they are either given to vendors, or sold exclusively to them for testing.   Motorola uses XC, or XPC for these, and unlike AMD/Intel, mass produces these and sells them, often for years, before they decide that a part/design is truly fully qualified/characterized (in which case the prefixe is changed to MC. or MPC).  Texas Instruments uses the ‘TMX” prefix for their Qual. Samples. and tended to make/sell them like Motorola did with theirs, changing the prefix to TMS for fully qualified production parts.

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July 3rd, 2018 ~ by admin

CPU of the Day: The Intel Everest Series

Mt. Everest – Tallest on Earth

Mt. Everest is the tallest mountain here on Earth, the pinnacle of climbing challenges.  There is no going higher then Mt. Everest.  At Intel the pseudo-unofficial codename for the absolute fastest speed bin of a particular processor is…Everest.  Everest processors are the fastest an architecture will so reliably.  Sometimes these processors end up an normal products, available for consumers to purchase.  The first good example of this is the Core 2 Extreme QX9775 Yorkfield core (Core Architecture).  They were a quad-core processor running at 3.2GHz, fast but not mind blazingly so.  The Xeon equivalent was the X5492 (Harpertown) 4-core at 3.4GHz.

Xeon X5698 – Westmere – 4.4GHz – Mid 2010

The next well know Everest was a chip based on the Westmere (shrink of Nehalem) architecture.  The Westmere Everest became known as the Xeon X5698, and was available for OEMs only, in fact it was a special order processor made with one particular type of client in mind. These were to be used for High Frequency Stock traders, and other such high speed transactional processing, where the ability to complete trades as fast, and reliability as possible is the entire nature of the business.  This means that single thread performance is far more important then having multiple core, and as such, the X5698 uses a 6-core die with only 2 cores active, but retaining access to the entire 12MB of L3 cache.  Clock speed was fixed at 4.4GHz, the cores did not reduce frequency as processing demands changed, as this would introduce uncertainty in how fast it would complete a given task. Doing task ‘X’ should take a predictable amount of time and not depend on what speed the processor chose to run at.  The next fastest Westmere processor was the X5690, which was a 6-core (all cores enabled) running at 3.46GHz (the same chip essentially as the Core i7 990X).  The X5698 was nearly 1GHz faster.  The X5690 cost around $1800, where as the X5698 cost around $20,000 EACH (based on costs OEMs charged to add a 2nd one so they may have marked it up some).  The impressive thing is that these chips would go faster.  Intel sampled 4.66GHz versions and Supermicro built systems using X5698’s overclocked to 4.8GHz.  All this back in 2011.

4.4GHz Jaketown (Sandy Bridge) Everest Sample 2010-2011

Intel’s next architecture was known as Sandy Bridge.  Sandy Bridge topped at at 3.5GHz (6-cores) for the Core i7 Extreme 3970X and 3.6GHz for the 4-core i7-3820 and similar Xeon E5-1620.  Intel demo’d an air cooled Sandy Bridge running on stage for a presentation at 4.9GHz, so the core certainly had some room to spare.  There is no documentation (that I could find) that Intel actually released anything faster then 3.6GHz, at least that I could find, but evidence suggests that they at least were thinking about it.  The picture is a Sandy Bridge Xeon in LGA2011 marked JKT EVEREST SS 4.4GHZ INTERNAL USE ONLY. JKT is short for Jaketown, Intel’s codename for the 32nm Xeon E5-2600 series.  That gives a very good idea what this processor was to be.  SS is likely to be a Single Socket (as often at those speeds getting dual systems working can be tricky).  Sandy was certainly capable of hitting 4.4GHz, with 4-core, and even air cooling, so perhaps these were samples for a limited OEM run, much like the previous Westmere X5698 processors.

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March 24th, 2018 ~ by admin

Making MultiCore: A Slice of Sandy

Intel Sandy Bridge-EP 8-core dies with 6 cores enabled. Note the TOP and BOTTOM markings (click image for large version)

Recently a pair of interesting Intel Engineering Samples came to The CPU Shack.  They are in a LGA2011 package and dated week 33 of 2010.  The part number is CM8062103008562 which makes them some rather early Sandy Bridge-EP samples.  The original Sandy Bridge was demo’d in 2009 and released in early 2011.  So Intel was making the next version, even before the original made it to market.  The ‘EP’ was finally released in late 2011, over a year after these samples were made.  Sandy Bridge-EP brought some enhancements to the architecture, including support for 8-core processors (doubling the original 4).  The layout was also rather different, with the cores and peripherals laid out such that a bi-direction communications ring could handle all inter-chip communication.

Sandy Bridge-EP 8-core die layout. Note the ring around the inside that provides communications between the peripherals on the top and bottom, and the 8-cores. (image originally from pc.watch.impress.co.jp)

Sandy Bridge EP supports 2, 4, 6 and 8 cores but Intel only produced two die versions, one with 4 cores, and one with 8 cores.  A die with 4 cores could be made to work as a dual core or quad, and an 8-core die could conceivably be used to handle any of the core counts.  This greatly simplifies manufacturing.  The less physical versions of a wafer you are making, the better optimized the process can be made.  If a bug or errata is found only 2 mask-sets need updated, rather then one for every core count/cache combination.  This however presents an interesting question..What happens when you disable cores?

That is the purpose of the above samples, testing the effects of disabling a pair of cores on an 8-core die.  Both of the samples are a 6-core processor, but with 2 different cores disabled in each.  One has the ‘TOP’ six cores active, and the other the ‘BOTTOM’ six cores are active.  This may seem redundant but here the physical position of the cores really matters.  With 2 cores disabled this changes the timing in the ring bus around the die, and this may effect performance, so had to be tested.  Timing may have been changed slightly to account for the differences, and it may have been found that disabling 2 on the bottom resulted in different timings then disabling the 2 on the top.

Ideally Intel wants to have the ability to disable ANY combination of cores/cache on the die.  If a core or cache segment is defective, it should not result in the entire die being wasted, so a lot of testing was done to determine how to make the design as adaptable as possible.  Its rare we get to see a part from this testng, but we all get to enjoy its results.

March 15th, 2018 ~ by admin

CPU of the Day: Intel Jayhawk – The Bird that Never Was

Intel Jayhawk Thermal Sample – 80548KZ000000 QBGC TV ES – Made in April 2004 Just 3 weeks before it was canceled

Perhaps fittingly the Jayhawk is not a bird, but rather a term used for guerilla fighters in Kansas during the American Civil War.   It is also the name of a small town in California 150 miles Northeast of Intel’s headquarters in Santa Clara.  It was also the chosen code name for a Processor Intel was working on back in 2003.  In 2003 Intel was working on the Pentium 4 Prescott processor, to be released in 2004 and its Xeon sibling, the Nocona (and related Irwindale),  The Prescott was a 31 stage design made on a 90nm process.  There was hopes it would hit 4+ GHz but in production it never did, though overclockers, with the help of LN2 cooling were able to achieve around 8GHz.  Increasing the length of the pipeline helps allow higher clock speeds, the Northwood core had a 20-stage pipeline so the Prescott was a rather big change.  There is a cost of lengthening the pipe, processors don’t always execute instructions in order, often guessing what will come next to speed up execution.  This is called speculative execution, processors also guess what data is to be needed next, and stick it in cache.  If either of these ‘guesses’ is wrong, the processor needs to flush the pipeline and start over, at a comparatively massive hit in performance.  This is what performance doesn’t always scale very linearly with clock speed.

Intel figured that this wouldn’t be an issue and so the Prescotts successor was to have a 40-50 stage pipeline.   THe hopes were for 5GHz at 90nm and 10GHz at 65nm. The desktop version was known as Tejas, and the server version, Jayhawk.  Initially these were to be made on the 90nm process, same as Prescott, before being transitioned to a 65nm process.  It increased the L1 cache to 24k (some sources say 32k) from the Prescotts 16k.  The Instruction trace cache was still 16k micro-ops, though this could have been increased.  L2 cache would have been 1MB at introduction and 2MB once the processor moved to a 65nm process.  Eight new instructions were to be added called ‘Tejas New Instructions’ or TNI, these later would become part of the SSSE3 instructions released with the Core 2 processor.  It also would bring ‘Azalia’ Intel’s High definition audio codec, DDR2 support, a 1066MHz bus, and PCI-Express support.  It turns out there was a problem….

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November 24th, 2017 ~ by admin

New Test Board Available for Sale: Intel 3002 Bit-Slice Processor

3002 Test Board

We have released a simple (its our least expensive board yet) Test Board for the Intel 3002 Bit-Slice Processor.  The Intel 3000 bit-slice processor family was introduced in 1973 and were made on a  Schottky Bipolar process. The 3002 series was also second sourced by Signetics, Siemens, and Intersil, and clones were made by the USSR and Tesla  (Czech).  The 3002 CPE is a 2-bit ALU and register file that can perform logical and arithmetic operations, left/right shifting and bit/zero value testing. The 3002 also includes 11 registers (R0-R9, T), an accumulator and a Memory Address Register (MAR). The 3002 CPE elements execute micro instructions generated by the 3001 Microprogram Controller Unit (MCU) based on micro code stored in PROM.
Its only $69.95 (including FREE shipping worldwide)

Order it on the 3002 test Board page.

In other related news, we are also developing a test board for some other BSP. Hopefully we’ll have a single board (with expansions) that can handle AMD 2901/03/203 and MMI 6701 processors

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Products

August 17th, 2017 ~ by admin

Intel Broadwell Broadens its Horizons…In Space

SpaceX CRS-12 – Carrying 116lbs of High performance Broadwell computers (image: SpaceX)

Monday’s launch of a SpaceX Falcon 9 rocket carrying a Dragon spacecraft to the space station carried what will be the most powerful computer in orbit.  In a joint project with HPE (HP Enterprise) NASA wants to test how high end computers, with off the shelf parts and construction perform in low Earth orbit.  The computer that will be soon installed is an HP Apollo 40 series (exact model is unclear, probably PC40/SX40).  It consists of 2 1U dual socket systems, running Intel Xeon E5-26xx V4 (Broadwell-EP 14nm) processors and supporting infiniband.  The only modification done was to use liquid cooling vs air cooling as the EXPRESS racks on the ISS are not set up to handle the heat load the computer generates.  The computers run on a standard 110VAC supply, provided by a NASA supplied inverter, which takes the 48VDC power generated by ISS’s solar arrays and converts it to the 110VAC needed by the Apollo computer.

The Broadwell processors are made on a 14nm process, and are some of the latest made by Intel (NASA froze the design in March so they were the fastest available to HPE at that time).  Performance will be just over 1Teraflop, a great increase over the main computers that actually RUN the ISS, which are Intel 80386SX based.  The astronauts themselves use laptops of various pedigrees, mainly Lenovo Core 2 Duo based A61Ps (these are being replaced by HP Zbook 15s powered by Intel 7th Gen Core i5 and i7 processors) , so the Apollo is a great leap up from them as well.

Mockup of HPE Apollo Computers for EXPRESS rack integrations. 2 computers with water cooling system between them.

To test the Apollo, NASA will run an identical system on the ground, performing the same tasks, and compare the outputs.  They want to see how the computers handle the environment in space, with various loads and electrical conditions.  One computer (both on the ground and on the ISS) will be run at maximum performance for the entirety of the experiment, while the other will have its computing/electrical load dynamically varied.

Radiation is usually one of the biggest concerns for space based computers, but on the ISS, radiation levels are not particularly high.  Daily doses experienced by the crewmembers are in the 10-50 millirad range. There are of course periods of higher radiation, either from where the ISS is in orbit, or from space weather.  The water cooling will further shield parts of the computer from radiation (water being a great radiation shield).  The Broadwell-EP processors have around 7.2 billion transistors, increasing the

10-core Broadwell die. Made on 14nm process.

chance that even a small amount of radiation may have an effect.  By running one set of computers at maximum performance, NASA can see these effects quickly.  Does the performance decrease? Does the power draw start spiking? Or is data being lost in the Infiniband networking PCIe card?

Currently experiment data has to be transferred to the ground in raw unprocessed format, as nothing on the ISS can handle the computing need to process it.  If the high performance computing experiment is successful, it can give the astronauts the ability to do processing and analysis of experimental data in orbit,. and transfer only the results to the ground, saving precious bandwidth, and allowing for experiments to be modified, changed, or created in orbit based on the ongoing results.

 

More Information: 

NASA: HPC COTS Experiment

HPE: The space station gets a new supercomputer

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Processor News

June 20th, 2017 ~ by admin

Intel’s First: The 3101 64-bit Bipolar Memory

Intel 3101 Memories, from late 1969 early 1970.

Today when we think of Intel, the ‘processor company’ comes to mind.  It was now what they are best known for, but when Intel began in 1969 they did not make processors, they made memory, specifically SRAM, DRAM, and EPROMs.  The very first product Intel released, in April of 1969, was the 3101 64-bit SRAM.  It was made on the new, and fast Schottky Bipolar process.  This made it very fast (access times of 60ns) but very power hungry.  It dissipated 525mW, over half a watt, for 64-bits of memory.

Two months later Intel released the 1101, which was developed at the same time as the 3101.  It was made on a PMOS process, which allows much greater densities, the 1101 was 256-bit SRAM chip.  The sacrifice is speed, the 1101 is a bit slow, with access times of around 1.5us.  Operating power was 700mW but in standby mode it only drew 350mW.

Very Early Burroughs “D” NanoMemory board with 32 Intel 3101 memories (picture from Evan Wasserman )

Computer makers were eager for single chip memories, they allowed for more dense memory systems.  One of the first users of the 3101 was Burroughs in their ‘D’ machine, a computer designed for the Air Force in 1969.  It used 3101s for its ‘nanomemory’ organized as 64×56 bits (needing 56 3101s if they were used for all the nanomemory.  Other notable users was in implementing the stack in the Datapoint 2200.  The 2200 is the grandfather of x86, its architecture was the basis for the Intel i8008, which then led to the 8080 and 8086 processors.  The first Xerox Alto’s also used the Intel 3101, arguably the first GUI implementation.

The 3101 evolved as Intel learned the process of making chips, and assembling them.  This is notable in looking at die shots of two 3101s with lot codes likely only a few months apart.  Ken Shirriff, a fellow collector, was donated a pair of 3101s nearly identical to those pictured, for decapping and die shots, by Evan Wasserman (who donated several to the CPU Shack Museum as well).  If addition to the package difference (not the larger lid on the later one) there is some die changes as well.  The bonding pads were made much larger, likely to ease the assembly, and the main VCC line on the top of the die was made smaller.  Connections to bond pads were also cleaned up and refined.  The logic of the device appears unchanged.

3101 dies. Left is lot 898, right is the later 1116. Click for much larger version. Die photos provided by Ken Shirriff

Through the 1970’s and well into the 1980’s memory devices were by far Intel’s largest revenue source.  It wasn’t until fierce competition in the memory market that this changed.  Had it not been for IBM adopting x86, things could have been much different and more difficult for Intel.  The rapid adoption of x86 gave Intel a new revenue stream, and one that was less likely to be pressured by commodification as was happening to memory devices.

 

 

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CPU of the Day

March 12th, 2017 ~ by admin

When Intel Runs out of Chips…..

Intel D80130-3 OSP – Engineering Sample – Early 1982

A seemingly impossible occurrence today, but something that Intel has faced in the past.  It is common for customers to need chips that are no longer in production, either for repair of legacy systems, or to keep an old but reliable design in production.  Typically these parts can be sourced on the secondary market, or from End-of-Life suppliers such as REI, or InnovASIC.  But what happens when Intel themselves needs a chip that they previously made, but no longer do?

Such was the case with the 80130 Operating System Processor.  The 80130 was a co-processor designed in 1981, to make use of Intel’s high-density ROM capabilities.  The 80130 contained 16K of ROM, 3 timers (compatible with 8254), an interrupt controller (similar to the 8259), and a baud-rate generator.  It was capable of bus management and control and could directly control an 8087 FPU as well.  These are designed to work with the 8086/88 and 80186/188 processors.  The 16K of ROM was coded with 35 Operating System primitives (a subset actually of the Intel iRMX86 RTOS (Real Time Operating System).  This firmware allowed easier support for the constructs typically used in a multitasking OS.  Essentially the 80130 extended the instruction set of the x86 to include higher level OS functions.

Intel D80130-2 – 1983 – Production version (though datasheets continued to be marked ‘Preliminary’ though its entire life)

The original version, called (for no known reason) the 80130-3 was released in engineering sample versions only.  It could run at up to 8MHz allowing it to work with any of the x86 processors of the time.  After some small timing adjustments, the 80130 was released to production as the 80130-2, still keeping with the 8MHz max.  Later references show a 80130 at 5MHz as well as the 8MHz -2 part.  However, the 5MHz part has not been seen (as of this writing) and is likely to exist only in datasheets.

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August 25th, 2016 ~ by admin

Intel i486 Prototype: Intel’s Gamble with CISC

Intel A80486DX SXE19 Engineering Sample - May 1989

Intel A80486DX SXE19 Engineering Sample – May 1989

The Intel 80486 was announced at COMDEX in April 11th 1989, justy 3 years after the 80386 hit the market.  The 80486 was really a greatly enhanced 80386. It added a few instructions, on-chip 8KB Write-Thru cache (available off chip on 386 systems) as well as an integrated FPU.  Instruction performance was increased through a tight pipeline, allowing it to be about twice as fast as the 80386 clock for clock.  Like the 80386 the 80486 was a CISC design, in an era when the RISC processor, in its may flavors, was being touted as the future of ALL computing.  MIPS, SPARC, and ARM all were introduced in the late 1980’s.  Intel themselves had just announced a RISC processor, the i860, and Motorola had the 88k series.  Intel in fact was a bit divided, with RISC and CISC teams working on different floors of the same building, competing for the best engineering talent.  Would the future be CISC, with the 80486? Or would RISC truly displace the CISC based x86 and its 10 years of legacy?

This dilemma is likely why Intel’s CEO, Andy Grove, was nearly silent at COMDEX.  It was only 4 years previous the Mr. Grove, then as President, made the decision to exit the memory market, and focus on processors, and now, a decision would soon loom as to which type of processor Intel would focus on.  Intel eventually ditched the i860 and RISC with it, focusing on the x86 architecture.  It turns out that ultimately CISC vs RISC didn’t greatly matter, studies have shown that the microarchitecture, rather then the Instruction Set Architecture, is much more important.

Intel A80486DX-25 - SX249 - B4 Mask from Sept 1989 with FPU Bugs

Intel A80486DX-25 – SX249 – B4 Mask from Sept 1989 with FPU Bugs

Whether due to the competition from the i860 RISC team, or knowing the markets demands, the 80486 team knew that the processor had to be executed flawlessly.  They could ill afford delays and bugs.  Samples of the 80486 were scheduled to be released in the 3rd quarter of 1989 with production parts shipping in the 4th quarter.  The above pictured sample is from May of 1989, a quarter ahead of schedule.  Production parts began to ship in late September and early October, just barely beating the announced ship date.

Perhaps due to the rush to get chips shipping a few minor bugs were found in the FPU of the 486 (similar to bugs found in the FPU of the 387DX).  Chips with the B4-Mask revision and earlier were affected (SX249).   These bugs were relatively minor and quickly fixed in the B5 mask revision (SX250), which became available in late November of 1989, still within Intel’s goal of the 4th Quarter.

The 80486 was a success in the market and secured CISC as the backbone of personal computing.  Today, the CISC x86 ISA is still used, alongside the greats of RISC as well.

December 6th, 2015 ~ by admin

T-5 Delivers DRAM’s – Intel Open House ’83

Memorabilia_Intel_OpenHouse-T-5

Intel DRAM – Likely a 2186 64K device given out during the 1983 Open House

In 1983 memory products were still Intel’s largest source of revenue.  Intel’s first product, the 3101, was a RAM, and until the memory trade wars of the early 80’s continues to be Intel’s bread and butter.  Fab 5, opened in Aloha, Oregon in October of 1978 and its primary product was memories.  EPROM’s, EEPROM’s, SRAM, and DRAM were all fab’d here, then shipped overseas, and back to Oregon for testing.  The primary testing facility for the Memory Products division was the T-5 site in Hillsboro, just a few miles from Fab 5.  T-5 tested both commercial, and military memory products up until 1985, when Intel exited the DRAM market in its entirety.

Intel Open House Chip form 1981 - Likely a 214x SRAM

Intel Open House Chip from 1981 – Likely a 214x SRAM

These OPEN HOUSE sample chips were handed out to employees and visitors at the test site during its annual open house in 1983 (apparently in many of the open houses at that time).  Most likely this chip is a 2186A integrated RAM, a 64K DRAM made on a 1.2 micron HMOS-III process.  The 2186 was a new design for 1985 and provided a DRAM with the same pinout as a 2764 EPROM.

Just like T-5, Intel DRAMs are no more, though the Fab 5 they were made in, which was closed in 1998, was reopened to increase Flash production, the only memory product Intel still makes.  Intel’s exit of the DRAM business was certainly a risky decision back then, but it turned out to be one of the best they made.  They blamed the exit on the rapidly falling prices do to ‘dumping’ of DRAM’s and EPROMs (sold below cost) from Japanese semiconductor companies, but this allowed them to exit the DRAM business before DRAM’s turned into the commodity they are today, with margins being almost non-existent.  This allowed Intel to focus time, resources (fab capacity was in very short supply then) and money on other products, namely microprocessors and microcontrollers, they very products that have taken Intel from a one of many semiconductor company to world leader.  Perhaps they can thank those same Japanese companies they were so upset about back in 1985 for where they are today.