Usually we find vintage processors here at the CPU Shack Museum, however, from time to time, we get our hands on something very new, and usually significant.  If by significant one means the processor from a Top500 supercomputer then yes, it is significant.

IBM 51Y7638 – Produced Early 2012 – Blue Gene/Q 1.6GHz 18 Core PowerPC-A2

This is a Compute card from an IBM Blue Gene/Q (specifically the 6 rack BG/Q running at England’s Science & Technology Facilities Council Daresbury Lab in Cheshire).  A Blue Gene/Q system is made up of these cards, 32 per ‘Node Card’, and 1024 per rack. This doesn’t count the I/O board which use a similar design and contains 8 Compute cards per rack.

BlueGeneQ ASIC die shot

Each of the Compute cards contains a large ASIC (the large chip in the middle).  This ASIC contains 18 PowerPC-A2 processor cores running at 1.6GHz.  16 of them are ‘User’ cores, 1 is for system management (handles interrupts  message passing, etc) and the 18th is a spare, for increased fault tolerance. The ASIC also contains 32MB of shared L2 cache and a dual 1.3GHz memory controller for the 16GB of DDR3 memory on the card.   All said this 45nm chip contains 1.47 Billion transistors, but only dissipates 55Watts, granted, that adds up when you have thousands of them.

A ‘basic’ system contains 4 racks, so 4096 compute cards (4128 if you count the the I/O boards). Together this is 65,536 user cores and consumes upwards of 85kW of power (this actually makes it one of the most efficient super computers available).

So how do these cards become available?  Simply put when you have so many in a system, statistically you are going to have failures, and somewhat frequently.  IBMs target failure rate, based on a 96 rack system (which is massive) is 70 hours.  That’s one failure  every 3 days.  At this point the common reaction is to express shock at the dismal reliability of such a system, however, lets put it another way, that’s one failure out of 98,000+ Compute cards (yes there are other failure points but for the sake of argument we’re using just the compute cards).  If you run an IT department that services nearly 100,000 computers and you only have to fix something twice a week, there is a good chance you should get a raise.

Click for much larger

Every now and then I will get a chip in that I cannot ID.  This is a particularly perplexing one.  It looks like it should be something fairly well known, but I cannot determine what.  By the dates its a 2005 vintage IBM, MCM, on a fairly large ceramic package with 1077 lands.  It contains a pair of Infineon HYB39S256160DT-7 256Mbit (4Mbitx16bit) DRAMs which are 7ns 143MHz max, commonly used on PC133 SDRAM.   That works out to 64MB.  Also on the package is a IBM0436A8ACLAB 8Mbit (256Kx36) 4.5ns (222MHz) 1Mbyte SRAM.

IBM MCM die

Markings on the die are:
0FE45000L3
AKESXEX0
1 10-10
09K2262

If you have any ideas what it is, or what it may be, post a comment.  I may just give you one.  These came in with a lot of HP PA-RISC processors, so perhaps related?

UPDATE (10/20/2016): Mystery solved. These are processors from a Cadence Palladium emulator system. Read more about them here

PIC17C766/CL ES

If there is anything a Microchip PIC is known for typically ‘large’ is not what comes to mind.  PICs were originally developed in the 1970s as a peripheral controller and ended up finding uses in products of every sort, for 35 years and counting.  The PIC17 series extended the original 12 bit architecture to 16 bits (16 bit instructions, ALU and registers are still 8-bit).  It added many new instructions (58 total) and an 8×8 hardware multiplier. Max clock speed was 33MHz. It was considered the ‘high end’ of the PIC line but now has been replaced by the PIC18 line.  Most of the PIC17s produced were in the 40-68 pin range. Many designers considered the PIC17 to be a less then great processor and in 2000 Microchip replaced it with the much better PIC18 line.

This PIC17C766/CL was one of only 7 variants in the line (17C42,43,44, 752,756,762 and 766) compared to the many dozens in the PIC16 or 18 lines.  Produced in an 84 pin CLCC with UV EPROM window (for its 16k EPROM) the 17C766 provided 66 I/O lines, more then enough for any project.  It was used in some PIC development systems and emulators which were some of the few systems that really needed a PIC with 84 pins.  This particular example also happens to be an Engineering Sample and was produced in mid-2001, AFTER the introduction of the PIC18, it seems there was still at least some demand and use for the PIC17 a decade after its introduction.

Intel 486 With new logo – 2007

Intel introduced the 486 in 1989, 24 years ago so it may be a bit surprising to see a 486 with the more modern Intel non-‘dropped e’ logo.  Intel began using the current logo in 2006, well after the height of the 486 market.  However Intel continued to make several 486 processors clear up through 2007.  These went to supply many embedded applications (medical, industrial, etc) that had originally been designed with a 486 and remained in production.  These types of devices either did not need a better processor or due to regulatory reasons, could not use one.  This is actually a common issue with medical devices, once designed, they are certified by the FDA (in the US, other agencies in the EU, Canada etc).  This certification is very specific to that exact hardware.  Often you cannot even change the S-spec/revision of the processor.  If it was built/certified with an SX911 A80486DX2-66 that’s what it must continue to use.  Re-certification is very expensive and time consuming.  It may seem overkill but these type of applications are often life sustaining, a failure could mean more then a reboot and lost game of Doom.  This is why Intel (and other companies) will choose a few products out of each line to be long-term production, this helps engineers select a product to design into their device, that has a guaranteed production life.  Currently Intel’s long term products guarantee a 7-year production.

Original DX2 Late 1994

This particular chip was made in April 2007. Intel announced it would be discontinued by the end of 2007 so this is truly one of the last (Intel) 486s ever made.  It is a SX911 &E5V2X version which is an SL Enhance (&E) 5 Volt Mobile (2X) processor.  The 2X means that the processor requires 2 external clocks, typically one would be used for when a laptop was plugged in (full speed, 33MHz in this case) and a second, which could be anything lower, for battery operation.  Obviously these can be implemented in any application, not just a laptop.  Registers contents, interrupts  etc are all preserved when the processor switches clock frequency so this is done on the fly, just like today’s processors.  The SX911 spec, which first was released in 1994, came in both 1X (desktop) and 2X (mobile) versions.  Throughout its 13 years of production it remained on a 150mm (6-inch) wafer process at 0.8u.

Cypress CY7C601-25GC – First package with heatspreader – Omitted on later versions

In Mid-1987 Sun Microsystems (now owned by Oracle) released the SPARC (Scalable Processor ARChitecture)  processor architecture to be used in their computers (replacing the 68k based systems they had previously used).  The SPARC was designed from the outset to be an open architecture, allowing manufactures to license and built processors that implemented it using whatever technology they wished.  The goal of this was to 1) build a large SPARC ecosystem and 2) keep prices in check by fostering competition among manufacturers.  The SPARC is still used today by Oracle, Fujitsu, the European Space Agency and others, owing largely to its design as an open architecture from the very beginning.

The first version was made by Fujitsu on a 20,000 gate array at 1.2 micron and ran at 16.6MHz.  In July 1988 Cypress  (later to be spun off as Ross and make the famous HyperSPARC line) announced the CY7C601.  This was the fastest implementation of the SPARC at the time.  It was made on 0.8u CMOS process and contained 165,000 transistors, dissipating around 3.3Watts.  As was typical of many processor designs of the time, it was an integer only processor, requiring a separate chip (the CY7C602) for floating point work.  In September of 1988, Cypress cross licensed the ‘601 to Texas Intruments in exchange for rights to the 8847 floating point processor.  This was mainly to appease one of Cypress main customers who demanded that a second source for the ‘601 chips be available, a demand more common in the 1970s then in 1988 but Cypress obliged.  Cyrpress also gained the rights to make the next generation SPARC processor that TI was developing.  TI would go on to make many SPARC processors, and continued to be the primary fab for Sun up through the SPARC T2 Plus in 2008.  Oracle now used TSMC to fab the T3 and T4 SPARC processors.

Welcome to 2013!  2012, was a busy year here at the CPU Shack Museum. We added 716 new processors/EPROMs/MCUs, which works out to an average of 2 new chips per day.  This includes 16 New in Box Processors. We also added 53 new Graphics Processors, which isn’t bad for something we only collect on the side.

Some processor highlights (in no particular order, click to enlarge):

Here is a HP/Compaq 21364 1300MHz, this was the end of the road for the DEC Alpha architecture.  It was killed off in favor of the Itanium, for better or for worse.

The IBM POWER5+ MCM is a stunning chip to look at, clocked at 1.9GHz its a dual core with on package L3 cache

An Intel MG80387-16 SM156 US Military MIL-STD-883B spec math co processor for the 80386 processor.  Made in 1990

Going back in time further is this East German (MME) 80A CPU, a clone of  the Zilog Z80 made in 1991 (copied before unification, produced after, for this example).  Its always neat to see the white ceramic package, even well into the 1990’s.

NexGen was a company that became victim of the wild processor wars of the 1990’s.  It was bought out by AMD which used its designs as the basis of the very popular and successful AMD K6.  Here is a very uncommon 133 (rated) without FPU.  Later they made a version with an integrated FPU.

And to get all the way to ‘Z’ we shall go to the Zoran ZR36762.  Its a DVD controller SoC, with Dolby Digital support.  Not something one sees and thinks of as a processor.  However at its core, even in 2004, it is not an ARM, its not a MIPs, its a high speed (67MHz) Turbo186, the same 186 architecture Intel released in 1982, still being used, albeit in CMOS.

In the next few days I’ll post some EPROM highlights, then some GPU highlights.  2013 is already off to a great start with new chips coming in each week.

Over two years ago we wrote about the history of the Signetics 8X300 processor.  A design that was one of the first DSP like architectures.  The 8X300 was a design of the Scientific Micro Systems Inc. SMS300.  You can read the entire history here.

The only SMS300 I had ever seen was a picture of one in the 1976 issue of Microcomputer Digest (as seen here).  Its a very unusual package, with very long leads.  Recently I found one hiding in a scrap lot on eBay, and could nearly not contain my excitement when the seller confirmed its markings.  Of course I purchased the scrap lot, and waited  like a child before Christmas for it to arrive.  When it did, I was happily surprised to find it intact, and in good condition (a relatively rare occurrence for a DIP in a scrap lot, especially a 36 year old one.

SMS 300 – Early 1976

Here you can see an original SMS300 dating from 1976.  Interestingly enough the Signetics version is in a 50 pin package while the SMS is in a 48pin.  I assume Signetics changed some of the power supply requirements for it but do not know for sure.

Back side showing stunning traces and die caps

Looking at the back of the processor you can see 2 large ceramic ‘caps’, one is for the die, the other appears to be a power circuit of some sort.  These are over 2mm thick, which is one of the reasons for the very long pins. (8 mm long).  If you have any additional info on the SMS300 (a datasheet perhaps) please let me know.

Cyrix Joshua Sample

Perhaps one of the most confusing, and misreported processor stories is that of the Cyrix Joshua processor.  More correctly known as the VIA Cyrix III Joshua.  Cyrix began sampling this successor to the MII in 1999, a tumultuous time in Cyrix’s history, as they were in the midst of being sold to VIA by National Semiconductor.  The Joshua never made it into full production, being quickly killed off by the Centaur designed Samuel core. Centaur was the processor division of IDT which produced the Winchip series, bought by VIA only a month after their purchase of Cyrix.

Adding to the confusion was Cyrix bountiful use of code names for its upcoming products, with many seeming to overlap, change or be redundant.  Understanding the methodology of their naming will greatly increase ones understanding of the products.  Cyrix used a code name for the core of a processor, as well as a separate name for what application that core was going to be used in.  Just like Intel used the P6 core for the PII, Celeron, and Xeon, Cyrix intended its cores to be able to be used in several products.

In the late 1990’s Cyrix had two new cores under development.  The first was the Cayenne, an evolution of the 6x86MX/MII processor.  The Cayenne was essentially an MII, with a dual (rather then single) issue FPU, support for 3DNow! instructions, and perhaps most importantly, a 256K 8-way associative on-die L2 cache.  It retained the 7 stage pipeline of the MII, the 256 byte scratch pad L0 cache, an almost identical X-Y integer unit and the same 64K L1 cache.  Cyrix had had industry leading integer performance, but always lagged in the area of FPU performance.  The dual issue FPU was their attempt to help remedy this.  However, FPU intensive benchmarks, such as Quake 3, showed the Cayenne core to be about half as fast as a Celeron of equal rating (500MHz vs PR500 Cyrix).  Business apps, heavy in integer and light on floating point, showed the integer strength of the Cyrix, with a 400MHz Cyrix matching a 500MHz Celeron.

The Cayenne core was slated to be used in at least 3 different products.  The first was the MXi, this was the successor to the MediaGX and thus would be highly integrated, including a PCI Bus controller, SDRAM controller, MPEG/DVD acceleration, 2D/3D Graphics as well as audio capabilities. The Jedi was to be a socket 7 (Super 7 really) compatible processor based on the Cayenne core.  This was canceled in 1999 (nothing to do with potential lawsuits from Lucas Films as often was rumored).  The third use of the Cayenne core was the Gobi, this was to be a Socket 370 compatible processor and it is this version that was widely sampled, and benchmarked, by many hardware review sites, magazines, etc.  When VIA purchased Cyrix on June 30, 1999 the Gobi project was allowed to continue, MXi, and other projects were quickly shut down.  The Gobi codename did not fit with VIAs core naming scheme however, thus is was renamed.

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Fairchild F9450 – 1985 – 10MHz

In 1980 the United States Air Force published a standard for a 16-bit Instruction Set Architecture (ISA) to meet their needs for computers on fighters etc.  This standard is known as MIL-STD-1750A and laid out what the processor needed to be able to do, but not how, or what would be used to accomplish it.  This allowed manufacturers to implement the standard in anyway they wanted.  It could be done in CMOS, Bipolar, SoS, GaAs or even ECL.  It was designed (like the Signetics 8X300 and the Ferranti F100) with real time processing in mind, similar to what we would call a DSP today.

Many companies made 1750A compatible processors including Honeywell, Performance Semiconductor (now Pyramid), Bendix (Allied), Fairchild, McDonnell Douglas, and others.  The processors ended up finding uses in many things outside of the USAF, including many satellites and spacecraft including the Mars Global Surveyor.  The standard was not restricted to military use, in fact commercializing it was encouraged, as this would increase production, which would help decrease costs for the military.

Fairchild designed the F9450 to meet both the commercial, and military markets.  Initial availability was in 1985 and the F9450 provides an on-board floating point unit, an optional, second chip, on other implementations.  Fairchild also made a F9451 MMU (Memory Management Unit), and a F9452 BPU (Block Protection Unit).  The 9450 was manufactured in a bipolar process (Fairchild called it I³L for Isoplanar Integrated Injection Logic).  This helped boost speed, as well as greatly increased reliability, as bipolar is much less susceptible to higher radiation levels then CMOS is.  Bipolar processes also generate heat, lots of it and to help counter this Fairchild used a somewhat unusual (for a processor) ceramic package made of Beryllium Oxide (BeO).  BeO has a higher thermal conductivity than any other non-metal except diamond, and actually exceeds that of some metals. Normally the ceramic on a CPU package is some form of Alumina (Al2O3).  Beryllium itself is a carcinogen so grinding, or acid application on BeO is not recommended.  The bottom of the the 9450 was made with a different ceramic, as the goal was to get the heat away from the chip, and not back into the PCB.  9450s were available in speeds of 10, 15 and 20MHz and in Commercial, or Military temperature rating.  MIL-STD-883 screening was of course available.

By 1996 the 1750A architecture was declared inactive and not recommended for new designs.  However, due to its extensive software support, reliability, and familiarity, it enjoys continued use, and is still being manufactured by several companies.

MicroModule Systems GV1-D0-3S-60-120A 120MHz (top side)

MicroModule Systems (MMS) began operations in 1992, following the completion of an agreement to acquire the assets and license rights to the technology of Digital Equipment Corporation’s MCM (Multi-chip Module) engineering and manufacturing business in Cupertino, California. The MicroModule Systems vision was to lead the next wave of electronic integration technology. Previous waves have been: discrete components (1950s), integrated circuits (1960s), large-scale integration (1980s), and system on a chip (mid 1990s).

The MMS Gemini was a module, that includes the National Semiconductor chipset die (x2) , a P54CSLM Pentium die, tag RAM, and cache RAM (128Kx2) as well as an LM75A temperature sensor for thermal management.   MMS used Intel D0 revision P54 processors (with the exception of some early C0 die), a stepping Intel never packaged themselves (it was solely used for the ‘known good die’ program).  When Intel discontinued selling fully tested dies, MMS had no way to build the Gemini and later MMX modules, so in 1998 went out of business. The Gemini was used in many mobile, and rugged PC applications such as the Motorola MW520 Computer used in many police cars.

MMS also produced MCM modules for ROSS, used to make the HyperSPARC processor as well as the Intel Pentium Pro 1MB MCM.   For a company that was only in existence for 6 years, their impact was tremendous. MMS was not alone in their production of Intel Pentium Processor modules…

Fujitsu also made modules using Intel dies.  These were again used in rugged PC applications, laptops, and industrial computers.

Fujitsu MRN-3546 120MHz

Fujitsu made 100, 120, 133, and MMX processors on a MCM type package where the individual components are bonded/soldered to a ceramic substrate (rather then the PC Board)