August 10th, 2014 ~ by admin

An Interesting Fujitsu MCM Pentium Module

Fujitsu MRN-3545 (100) 100MHz Pentium with no L2 Cache

Fujitsu MRN-3545 (100)
100MHz Pentium with no L2 Cache

We have seen Fujitsu MCM Pentiums before.  120MHz, 133MHz 150MHz and MMX ones.  One is pictured in the article on the MicroModule Systems Gemini here.  The 100MHz module is similar, though it is missing the L2 cache tag RAM (256 kbit chip on the top of the package) as well as the 2 cache RAM chips normally installed on the backside of the module.  It would appear that Fujitsu offered these modules with the cache being optional.  There was a 133MHz version (MRN-3548) with cache, and one (MRN-3549) without cache.

These processors were typically used in environmentally challenging environments.  Panasonic famously used them in their ToughBook CF25, the beginning of a line of highly durable laptop in 1996.  Some of these applications were sealed environments, they did not have vents, or active cooling.  This obviously  makes cooling a challenge.  Removing the L2 cache, while causing a significant hit in performance, would alleviate some of the heat generation.

We consider L2 cache to be essential, but many applications do not require it.  Intel infamously removed the L2 Cache completely from the first Celeron processors and while they worked, they were not particularly competitive performance wise.  When competing against wind, rain dirt, and droppage? L2 cache may not be so important

March 11th, 2014 ~ by admin

IBM z800 MCM Mainframe Processor

IBM z800 MCM

IBM z800 MCM

Mainframes are the workhorses of the computing industry.  They process transactions for about every industry, and handle the brunt of the economy.  Their MTBF (Mean Time Between Failures) is measured in decades (typically 20-50 years).  A comparison to a home computer is hard to make, they are in an entirely different league, playing an entirely different game.

Data Intense vs. CPU Intense

Mainframe processors such as these work in what is referred to as ‘Data Intensive’ computing environments.  This is different from multi-cored processing that focuses on ‘CPU Intensive’ computing.  CPU intense has a relatively small data set, but most perform a lot of work on that set of data, or do the same instruction on a set of data (such as graphics).  CPU Intense processing can often be sped up with the addition of more processing cores.  Data Intense processing does not see as much benefit from adding cores.  Its biggest bottleneck is accessing the data, thus the System z tends to have VERY large caches, and very high bandwidth memory.  They typically operate on transactional type data, where the processing has to operate in a certain order (A has to be done before B which has to finish before C etc).

IBM was one of the first, and continues to be one of the largest suppliers of such systems.  Starting with the System/360 introduced in 1964 to the zSeries today.  The zSeries was first launched in 2000 with the z900, a significant upgrade from the System/390.  Data addressing was moved to 64-bits (from 31 bits) yet backwards compatibility (all the way back to the 360) is maintained.  The z900 ran at 775MHz and was built with a 35 die MCM containing 20 Processing Units (PUs) and 32MB of L2 Cache.

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February 18th, 2014 ~ by admin

CPU of the Day: IBM POWER5+ QCM

IBM POWER5+ QCM - 4 dies, 8 cores, and 72MB of L3 Cache

IBM POWER5+ QCM – 4 dies, 8 cores, and 72MB of L3 Cache

When the POWER5 processor was released in 2004 it was made in two versions, a DCM (Dual Chip Module) containing a POWER5 die and its 36MB L3 cache die, as well as a MCM containing 4 POWER5 die and 4 L3 cache dies totaling 144MB.  The POWER5 is a dual core processor, thus the DCM was a dual core, and the MCM an 8 core processor.  The POWER5 contains 276 million transistors and was made on a 130nm CMOS9S process.

In 2005 IBM shrank the POWER5 onto a 90nm CMOS10S manufacturing process resulting in the POWER5+.  This allowed speeds to increase to 2.3GHz from the previous max of 1.9GHz.  The main benefit from the process shrink was less power draw, and thus less heat.  This allowed IBM to make the POWER5+ in a QCM (Quad Chip Module) as well as the previous form factors.  The QCM ran at up to 1.8GHz and contained a pair of POWER5+ dies and 72MB of L3 Cache.

The POWER5+ was more then a die shrink, IBM reworked much of the POWER5 to improve performance, adding new floating point instructions, doubling the TLB size, improved SMP support, and an enhanced memory controller to mention just a few.

The result? A much improved processor and a very fine looking QCM.

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August 8th, 2013 ~ by admin

How To: Disassembling an IBM POWER4 MCM

The  IBM POWER4 was released in 2001.  It was a 1.1-1.9GHz dual core processor widely used in IBM’s server line including the RS/6000 and AS/400.  It can be commonly found as a single chip dual core, but also as a large MCM containing 4 POWER4 dies. These MCMs include a very large and heavy aluminium heatsink attached to a solid copper housing.  The complete unit weighs in at a hefty 3kg.  The heatsink and housing can be removed revealing a 230 gram MCM (with its small heat spreaders).

IBM POWR4 MCM disassembly

To disassemble one of these you will need a variety of tools.  A 4 mm socket, hex bits (2.5, 3 and 4mm), T8 torx bit , a medium flat tip screw driver, gloves and a good heat source (I use a propane torch)

Remove the Interposer and screws

First remove the 4 T8 torx screws that hold the interposer to the module.  It gets in the way and can melt easily.  Also remove the 8 3mm screws around the perimeter.  These hold the aluminium heatsink to the copper housing.

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March 13th, 2013 ~ by admin

IBM 3081 TCM Miniature Pendant

IBM 3081 TCM Pendant

IBM 3081 TCM Pendant

A few times I get things that are not processors but are memorabilia and are pretty special nonetheless.  Today these nice IBM pendants came in.  They are very small, measuring barely 37mm square but they weigh an impressive 60 grams.  They are a near perfect miniature version of a not so miniature IBM TCM (Thermal conduction module).  The 3081 TCM contained the cooling, and a very large MCM used in the 308x mainframe series (made from 1980-1987).  Each MCM contained up to 133 dies on a very large ceramic substrate with up to 16,000 contacts for the dies.  They were capable of speeds of up to 38MHz.  Each TCM was liquid cooled and dissipated around 300 watts of heat. A typical 308x system had 2 dozen of these.

A similar IBM MCM can be seen here: (a 9121 processor)

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Just For Fun

February 7th, 2013 ~ by admin

CPU of the Day: Unknown IBM MCM – Any ideas?

IBM MCM

Click for much larger

Every now and then I will get a chip in that I cannot ID.  This is a particularly perplexing one.  It looks like it should be something fairly well known, but I cannot determine what.  By the dates its a 2005 vintage IBM, MCM, on a fairly large ceramic package with 1077 lands.  It contains a pair of Infineon HYB39S256160DT-7 256Mbit (4Mbitx16bit) DRAMs which are 7ns 143MHz max, commonly used on PC133 SDRAM.   That works out to 64MB.  Also on the package is a IBM0436A8ACLAB 8Mbit (256Kx36) 4.5ns (222MHz) 1Mbyte SRAM.

IBM MCM die

IBM MCM die

Markings on the die are:
0FE45000L3
AKESXEX0
1 10-10
09K2262

 

If you have any ideas what it is, or what it may be, post a comment.  I may just give you one.  These came in with a lot of HP PA-RISC processors, so perhaps related?

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December 3rd, 2012 ~ by admin

GPU of the Day: SGI GE7 Geometry Engine

SGI Extreme 4GE7MCM 256 MFLOPS 320,000 Gates

At 2.6oz (75 grams) and 2.25 inches square (6cm) the SIG 4GE7MCM is a beast of a graphics chip.  More properly called a Geometry Engine was, the GE7 was responsible for all the graphics processing in SGI Indigo2 workstations.  The Indigo2 Extreme graphics option consisted of a pair of these MCMs (Multi-Chip-Module).  Each one contains 4 GE7 Geometry Engines providing 32MFLOPS of performance each.  Each GE7 consists of a custom 80,000 gate array from LSI (for a total of 320,000 gates and 128MFLOPS per MCM).  This performance level was, ironically, better then the main system CPU (35MFLOPs for the 200MHz R4400 option).

Each of the black ‘caps’ on the chip covers a single GE7 Engine.  A similar design was used for the XZ Graphics system that had only 4 total GE7 cores.  This was either implemented with 2 of the large MCMs that had only 2 GE7s in them (same package however) that were marked 2GE7MCM, or, later, a single surface mount MCM containing 4 GE7 engines.  All were manufactured by LSI.  In total the Extreme Graphics subsystem had no less then 31 custom gate arrays from LSI for a total of over 1.2 million gates.   At an average of 2 transistors per gate that works out to around 2.5 million transistors, a considerable amount for a graphics system in 1993.  Today’s graphics chips pack in transistors numbering in the billions, the Geforce GTX 680 has a total of 3.54 billion transistors, and performance measured in TFLOPS, again for the GTX 680, 3.09TFLOPS.  Today’s graphics chips cannot, however, compete with the magnificent looks of the GE7’s giant MCM package.

Sources:
Indigo2 Product Guide (PDF)
Indigo2 Technical Report 

 

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September 21st, 2012 ~ by admin

CPU of the Day: MicroModule Systems Pentium Gemini

MicroModule Systems GV1-D0-3S-60-120A 120MHz (top side)

MicroModule Systems (MMS) began operations in 1992, following the completion of an agreement to acquire the assets and license rights to the technology of Digital Equipment Corporation’s MCM (Multi-chip Module) engineering and manufacturing business in Cupertino, California. The MicroModule Systems vision was to lead the next wave of electronic integration technology. Previous waves have been: discrete components (1950s), integrated circuits (1960s), large-scale integration (1980s), and system on a chip (mid 1990s).

The MMS Gemini was a module, that includes the National Semiconductor chipset die (x2) , a P54CSLM Pentium die, tag RAM, and cache RAM (128Kx2) as well as an LM75A temperature sensor for thermal management.   MMS used Intel D0 revision P54 processors (with the exception of some early C0 die), a stepping Intel never packaged themselves (it was solely used for the ‘known good die’ program).  When Intel discontinued selling fully tested dies, MMS had no way to build the Gemini and later MMX modules, so in 1998 went out of business. The Gemini was used in many mobile, and rugged PC applications such as the Motorola MW520 Computer used in many police cars.

MMS also produced MCM modules for ROSS, used to make the HyperSPARC processor as well as the Intel Pentium Pro 1MB MCM.   For a company that was only in existence for 6 years, their impact was tremendous. MMS was not alone in their production of Intel Pentium Processor modules…

Fujitsu also made modules using Intel dies.  These were again used in rugged PC applications, laptops, and industrial computers.

Fujitsu MRN-3546 120MHz

Fujitsu made 100, 120, 133, and MMX processors on a MCM type package where the individual components are bonded/soldered to a ceramic substrate (rather then the PC Board)

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August 30th, 2012 ~ by admin

“We are hitting the limits of physics in many cases” – IBM zEC12 5.5GHz

z12 MCM Layout

“We are hitting the limits of physics in many cases”  These words, spoken by an IBM engineer about the new zEnterprise EC15 mainframe do well to describe the processor that runs it.  The z12, as we’ll refer to this processor, replaces the z196 as IBM’s top performer.  The z196 ran at a slothly 5.2GHz, the fastest commercial processor in the world until now.  The z12 runs at 5.5GHz and was designed to be clocked up to 6GHz.  It is made on a 13layer 32 nm High-K process (the z196 was made on a 45nm process).  This allowed a doubling of logic and cache density.

The EC12 is designed  with single thread performance in mind.  While many systems today focus on massive parallelism, and optimizing code for multi-threading, some tasks do not work well that way, data analytics, batch processing etc, are fundamentally serial processes, so less cores, and more speed per core is far more important.  The z12 is based on a MCM (Multi-chip module) that contains 6 Processing Units (PUs) and 2 Storage Controllers (SC, which contain 196MB of L4 cache each) for a total of 8 dies on each MCM.  Each PU contains 4, 5 or 6 active cores.  The MCM is a 103-layer glass ceramic substrate (size is 96 x 96 mm) containing eight chip sites and 7356 land grid array (LGA) connections.

IBM zEC12 6-core PU – 2.75 Billion Transitors – 5.5GHz

Each PU chip has 2.75 billion transistors. Each one of the six cores has its own L1 cache with 64 KB for instructions and 96 KB for data. Next to each core resides its private L2 cache, with 1 MB for instructions and 1 MB for data respectively.

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