Archive for the 'Boards and Systems' Category

January 18th, 2019 ~ by admin

Part 4: Mini-Mainframe at Home: Benchmarks and Overclocking

Part 4 of the Story of a 6-CPU Server from 1997.  In this final section we will first explore (briefly) the theory of running a 6-CPU SMP system (with processors designed for 2 or 4 way) and then move to benchmark the system and overclock it.

For the background of the ALR 6×6 and Pentium Pro processors that form the basis of this project please see:

Previous Parts of the Series

Part 1: Mini-Mainframe at Home – Introduction
Part 2: Mini-Mainframe at Home: Installing a Modern OS
Part 3: Mini-Mainframe at Home: The ALR 6×6 Hardware and BIOS

Features of the architecture and operation of the six CPU

So, as the server was originally shipped with six Pentium Pro “Black” processors, I decided to add six Pentium Pro “Gold” processors with a frequency of 200 MHz and a 256 KB L2 cache for contrast. Such a volume is just four times smaller, and at the same time it will be interesting to check the effect of the cache in such a volume: six megabytes versus one and a half.  But before starting the tests, I will focus on the principle of interaction of six processors in this system. To overcome the limitations of Intel on building a system with more than four processors, ALR engineers with the support of Unisys suggested using an inter-processor interaction scheme using arbitration:

The theory behind this architecture is as simple as it is powerful. Inside new six-way systems are two Tri-6 CPU cards, A and B (Figure 1). Each of these cards is an independent, three processor ready SMP bus, complete with all logic Active CPR processor protection, and auto-recovery technology built on each CPU card. These two Tri-6 CPU cards are then plugged into a 64-bit parity SMP bus. This design keeps the processors closely coupled, just like a parallel bus architecture, without the related heat and design problems. A separate four-way interleaved memory card is attached to the bus, supporting a sustained data bandwidth of 533-MB per second. This bandwidth is ample to support two full PCI buses as well as an EISA bus bridge.

To overcome the logical limitations of the Pentium Pro chip, six-way servers use a unique expanded bus arbitration configuration referred to as Dynamic Orchestration. The best way to understand how this system works is to compare it to a typical four-way SMP architecture. On a four-way system, bus arbitration is implemented in a “round robin” fashion. That is, each processor has equal rights to the bus, and access is handled in an orderly fashion. For example, if all processors needed access to the bus, CPU 0 would gain access first, followed by CPU 1, CPU 2, CPU 3, and then back to CPU 0. If CPU 2 was executing a cycle, and both CPU 3 and CPU 1 requested use of the bus, control would first pass to CPU 3, before cycling back to CPU 1.

For purposes of this four-way arbitration, processors are identified using the two-bit ID code. The six-way solution borrows this convention, with some important modifications. Within each Tri6 CPU card, individual processors are identified using the two-bit ID code. This yields four possible combinations, although only ID codes 0 through 2 are needed. A chip on each Tri6 card handles the arbitration, following the “round robin” scheme found in a four-way system. In this case, however, the fourth processor has been replaced by a sort of “phantom” processor that actually represents the other Tri6 card:

The figure above shows the six-processor scheme of the server board ALR Revolution 6×6 and its clones. Thanks to this approach, the appearance of 8, 10 and more processor systems has become possible.

Building a chessboard from various models of Pentium Pro, I thought that I could not find a larger processor. Even the 32-core AMD Threadripper 2990WX next to the Intel Pentium Pro does not seem so big.

However, The CPU Shack sent me this photo. On the left is the engineering version of the Xeon Gold 6142 on the LGA3647 socket, on the right another engineering version, but already the Intel Xeon’a Phi in the same LGA3647 version. As you can see, the story is back to square one and perhaps all subsequent processors will not be placed on the open palm of the hand. Although the processors in the performance of LGA2066 is still far from Intel Pentium Pro.

Overclocking 6 cores together and separately

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January 16th, 2019 ~ by admin

Part 3: Mini-Mainframe at Home: The ALR 6×6 Hardware and BIOS

Part 3 of The Story of a 6 CPU Server from 1997 – In this section we’ll learn about the hardware and BIOS that makes the ALR Revolution 6×6 with 6 Pentium Pro Processors work.

For the background of the ALR 6×6 and Pentium Pro processors that form the basis of this project please see:

Part 1: Mini-Mainframe at Home – Introduction
Part 2: Mini-Mainframe at Home: Installing a Modern OS

Exterior and Interior

The size of the case is quite large for the desktop (and it came with wheels, so probably not good  to have rolling about ones desk), but relatively compact for servers of this class. The height of the server is – 68 cm, width – 32 cm and depth – 58 cm. The weight of the server starts from 52 kg. I have a complete server kit, but the case is missing, because, due to its size and weight, the shipping to Belarus would be around $ 400, if not more, so the photos of the appearance were taken from the Internet.
Editor’s Note: The empty case is currently serving as a kitchen counter at the CPU Shack Museum.  Its really THAT big 

The first thing that catches the eye is the information touch! LCD display, the task of which is to display all the information about the status of the six processors, RAM, temperature, status of hard drives and other vital information. Today, such informative displays are the norm, but 21 years ago I even could not imagine that such a thing ever happened. The front of the case also has two compartments, the upper one under 5.25” devices, such as CD-ROM’s, the lower one opened access to the cage with SCSI drives. Behind you can see 14 expansion slots, a cooling system and a cage with power supplies.

To ensure the operation of  the server, two power supplies are needed, which are connected to a special board in the cage. The third power supply unit is a spare one in case of a single power supply failure. It is allowed to install four power supplies with the connection of two pairs to a pair of electrical outlets for complete duplication of all functions providing the server power.

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January 14th, 2019 ~ by admin

Part 2: Mini-Mainframe at Home: Installing a Modern OS

Part 2 of The Story of a 6 CPU Server from 1997 – In this section we’ll try to get a modern OS running on the ALR Revolution 6×6 with 6 Pentium Pro Processors.

For the background of the ALR 6×6 and Pentium Pro processors that form the basis of this project please see Part 1 of the project.

Part 2: Installing and Using an OS

Before you start installing the OS, you need to select the correct kernel of the operating system. To do this, at the initial stage of installation, press the F5 key.

In this case, we choose – MPS Multiprocessor PC, since the other options simply do not fit, since this server naturally does not support ACPI. In general, I will advise anyone who makes such experiments by choosing a more “modern” OS, which is older than the hardware itself – to turn off ACPI support in the BIOS (if present). This simple action will keep your nerves decent.

Windows Server 2003 R2 Enterprise Edition was installed and, as I wrote above, the system had one working CPU core.

Next, an attempt was made to install the operating system from the operating system itself using the update method, but at the initial stage the Windows Server 2003 Enterprise Edition installer warned me that a multiprocessor configuration not supported by the operating system was used.

But there are many ways to install the OS. Alternatively, I tried the OS “transfer method” with a known-workable SMP configuration. Taking the ASUS P2L97-DS motherboard on an Intel 440LX chipset with a pair of Intel Pentium-II with a frequency of 450 MHz, which should be deprived of a hardware error and chose the “MPS Multiprocessor PC” core, but the installation process did not start at the stage of copying the original files, reaching until installation on the hard disk. At this point, the system hung, not reaching the choice of the installation source. Much has been tried, loops, different drives and RAM, but all to no avail. At this point, a single Pentium-3 was also hanging on the Asus P3B-F motherboard (Intel 440BX chipset).

In the end, I decided to take another board with two SLOT 1 connectors – Asus P2B-D (Intel 440BX chipset) and a pair of Intel Pentium-III. OS Windows Server 2003 R2 Enterprise Edition was safely installed, it remains to transfer it to a six-processor server. As a result, having moved the necessary hard drive, I decided to do the first boot in “safe mode” in order to exclude the influence of different devices of both systems on each other, but as a result I received a BSOD.

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January 12th, 2019 ~ by admin

Part 1: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997

Introduction

This article/project is provided in cooperation with guest author max1024, hailing from Belarus. I have provided some minor edits/tweaks in the translation from Belarusian to English.

As part of this project, you will have a unique opportunity to learn about a mini mainframe worth more than a Ferrari, which had enormous power by the standards of 1997, as well as the intricacies of installing a more modern operating system on it and other interesting details. I think that to some readers, the bold name of the super server ALR Revolution 6×6 already says something, and it will be discussed in this article.

Pentium Pro Processor versions – Minus the Overdrive

Alone, it would be simply not realistic for me to translate everything I had planned, without the help of my comrades from the United States, Russia and Great Britain, this project would have remained a project on paper, but their invaluable help would make it possible for the planned and almost forty kilograms of net weight (nearly 90lbs) to go a long way, more than 11 thousand kilometers (6800 miles) for three separate packages. The total distance as a result of which all the parts came together was 30 thousand kilometers (18,000 miles)  – for reference, the circumference of the Earth is 40 thousand km. (~25,000 miles)),  So this work is partly their merit, for which I am immensely grateful.

Editors Note: This ALR 6×6 came from the CPU Shack Museum, having sat in my house for some years. While chatting to Maksim last year he mentioned he would like to find one, so it was clearly meant to be.  You can’t just ship an ALR 6×6 across the world to Belarus, at least not economically, so over several months I disassembled the entire server and shipped it in pieces to a mutual friend in Russia, who then forwarded it to Maksim in Belarus.

Connor Krukosky and his IBM z890

Before embarking on the initial part of the project, I’ll tell you that trying to understand Mainframes and supercomputers  , I realized one thing that it’s quite possible to assemble even a “mini” mainframe at home, as Connor Krukosky did, but also overclocking would be even more interesting.

Studying such computational supermachines, I decided to dwell on systems consisting of Pentium Pro processors, so by installing Windows compatible applications and benchmarks, one could see how much the performance went ahead over the decades. Ideally, of course, it would be nice to get Intel ASCI Red, but I decided to start with its mini version.

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May 27th, 2018 ~ by admin

Mainframes and Supercomputers, From the Beginning Till Today.

This article is provided by guest author max1024, hailing from Belarus.  I have provided some minor edits/tweaks in the translation from Belarusian to English.

Mainframes and Supercomputers, From the Beginning Till Today.

Introduction

We all have computers that we like to use, but there are also more productive options in the form of servers with two or even four processor sockets. And then one day I was interested, but what is even faster? And the answer to my question led me to a separate class of computers: super-computers and mainframes. How this class of computer equipment developed, as it was in the past and what it has achieved now, with what figures of performance it operated and whether it is possible to use such machines at home, I will try to explain all this in this article.

FLOPS’s

First you need to determine what the super-computer differs from the mainframe and which is faster. Supercomputers are called the fastest computers. Their main difference from mainframes is that all the computing resources of such a computer are aimed at solving one global problem in the shortest possible time. Mainframes on the contrary solve at once a lot of different tasks. Supercomputers are at the very top of any computer charts and as a result faster than mainframes.

The need for mankind to quickly solve various problems has always existed, but the impetus for the emergence of superfast machines was the arms race of well-known superpower countries and the need for nuclear calculations for the design and modeling of nuclear explosions and weapons. To create an atomic weapon, colossal computational power was required, since neither physicists nor mathematicians were able to calculate and make long-term forecasts using the colossal amounts of data by hand. For such purposes, a computer “brain” was required. Further, the military purposes smoothly passed into biological, chemical, astronomical, meteorological and others. All this made it necessary to invent not just a personal computer, but something more, so the first mainframes and supercomputers appeared.

The beginning of the production of ultrafast machines falls on the mid-1960s. An important criterion for any machine was its performance. And here on each user speaks of the well-known abbreviation “FLOPS”. Most of those who overclock or test processors for stability are likely to use the utility “LinX”, which gives the final result of performance in Gigaflops. “FLOPS” means FLoating-point Operations Per Second, is a non-system specific unit used to measure the performance of any computer and shows how many floating-point arithmetic operations per second the given computing system performs.

“LinX” is a benchmark of “Intel Linpack” with a convenient graphical environment and is designed to simplify performance checks and stability of the system using the Intel Linpack (Math Kernel Library) test. In turn, Linpack is the most popular software product for evaluating the performance of supercomputers and mainframes included in the TOP500 supercomputer ranking, which is made twice a year by specialists in the United States from the Lawrence Berkeley National Laboratory and the University of Tennessee.

When correlating the results in Giga, Mega and Terra-FLOPS, it should be remembered that the performance results of supercomputers always are based on 64-bit processing, while in everyday life the processors or graphics cards producers can indicate performance on 32-bit data, thereby the result may seem to be doubled.

The Beginning

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November 22nd, 2017 ~ by admin

CPU of the Day: DEC LSI-11 Chipset

LSI-11 Chipset with EIS/FIS Chip – 1976-1977

Back in 2014 we discussed the Western Digital WD/9000 Pascal Microcomputer system.  Today we’ll look at the LSI-11 chip set, the basis of the Pascal.  Back in 1974 DEC (Digital Equipment Corporation) contracted Western Digital to design and build a 16-bit chipset to emulate the Bipolar PDP-11/05 Minicomputer.  Western Digital was paid $6.3 million for the work, and would be allowed to market and sell the resulting chipset themselves, as well as grant license to it to others (including DEC).

The LSI-11 was to be a 16-bit chipset, but was based around a 8-bit Data chips (the 1611).  The 1611 has an 8-bit ALU , 26 8-bit registers and a microinstruction register.  This is controlled by the 1621 control chip, which interprets macroinstructions from handles all the timing, as well as interrupts.  The 1621 control chip is what allows the 8-bit 1611 to be used as a 16-bit processor.  The chips are connected by an 18-bit  microinstruction bus, and a 16-bit address/data bus handles access to the rest of the system (memory/I/O).  Each microm is a 512 Word by 22-bit ROM, which can hold 80 instructions.  It is these MICROMs that allow the WD MCP1600 to function as a PDP-11/05.  The instructions in the the MICROMs (2 are required for the LSI-11) emulate the PDP-11 instructions.

DEC M7264 LSI-11 KD11-L Board from PPD- 11/03

First production of the LSI-11 chipset began in March of 1975 with shipments commencing that year.  The PDP-11/03 based on this chipset was released later that year.  The KD-11 M7264 board formed the hear of the 11/03 (as well as other DEC systems).  In typical DEC fashion it came in many flavors with different amounts of memory, as well as different instruction support.  This was completely due to the design of the LSI-11 chipset and its MICROMs .  The basic LSI-11 need 2 MICROMs to handle the basic PDP-11 instructions, the chipset however supported 4.  This mena that more instructions could be added.  One of the most common and useful additions was the EIS/FIS (Extended Instruction Set/Floating Point Instruction Set) microm.  This added 8 more instructions including MUL, DIV, FADD, FSUB, FMUL, FDIV and 2 register shifts (ASH, ASHC).  Adding the EIS/FIS chip to a standard KD-11-F board turned it into a KD-11-L (like the one pictured).

Western Digital 1611 Die –
Pauli Rautakorpi

There were other MICROMs available as well.  This included a set of 2 for support of DIBOL (Digital Business Oriented Language), a DEC language similar to COBOL.  Since the DIBOL chipset needed 2 chips a system could support DIBOL, OR EIS/FIS but not both.  MICROMs were revised as bugs were found, or faster ways of handing an instruction were made.  MICROMs revisions could also be made to support different PCB revisions.  In some ways they played the part of firmware to the PCB, as well as the instruction set for the processor.  In this way many MICROMs are specific to PCB etch revisions and other revisions of the system outside of the processor itself.  Matching the correct MICROMs, as well as Control and Data chips to the correct board is a bt of a task, and take several dozen pages of the LSI-11 maintenance manual.

Here are a few part #s to help sort things out

Data Chip
DEC 1611
Control Chip
DEC 2007C
MICROMs
MICROM 1 3010D/A
MICROM 2 3007D
EIS/FIS 3015D
Notes
21-11549-01 23-008B5-00 STD INST 1
21-15579-00 (1611H) 23-003C4-00 23-007B5-00 STD INST 2
21-16890-00 (1611H) 23-002C4-00 23-003B5-00 EIS/FIS
23-001C3 CP1621B14 23-009B5-00 EIS/FIS
23-001C2-01 CP1621B451 23-001B5-00 CP1631B103 STD INST 1
23-002B5 CP1631B073 STD INST 2
 23-091A5-01 CP1631B153 EIS/FIS
23-004B5 DIBOL 1
23-005B5 DIBOL 2
23-008A5-01 CP1631B-10 STD INST 1
23-007A5-01 CP1631B-07 STD INST 2

DEC M7270 LSI-11 – 1982 – All WD Chips

There are more to be found as DEC and Western Digital made many versions.  In early 1976 Western Digital licensed the MCP1600 chipset design to National Semiconductor, in exchange for some RAM technology licensing.  It is unclear if National actually made any of the MCP1600 chipset.  By 1977 DEC had started to produce the LSI-11 chip itself while continuing to source parts from Western DIgital as well.  It is common to see LSI-11 boards with DEC and WD chips mixed well into 1982.

The popularity of the PDP-11 in the 1970’s resulted in many customers for the LSI-11 based PDP’s, and their use continued well into the 1990’s with many systems continuing to be used today.  As with many such systems, they found use in industrial control and automation, where they continue to work.

March 29th, 2017 ~ by admin

TeraNex: Filling the GAPP

Teranex Piranha TN3260B – 1024 PE Array @ 64-90MHz

The GAPP (Geometric Arithmetic Parallel Processor) was designed in 1981 at Martin Marietta, which later became Lockheed Martin Electronics & Missiles.  It was funding in large part by the US Dept. of Defense as a way to develop technologies for ultra high-speed image processing.  There was a strong need for image processing, in near real time for military applications, in particular pattern recognition.  Being able to process a moving image and match its features to known patterns was very useful for targeting of many weapons system.

The GAPP processor was a massively parallel SIMD (Single Instruction Multiple Data) processor.  SIMD works very well on large sets of data that are processed in the same way.  In the design of GAPP, this data set was the 2D-array of an image, or frame, from a video.  The GAPP is at its core a very large array of simple processors, called processor elements (PE).  Each PE is relatively simple, containing a single bit ALU and registers/memory.  Each PE handles a single pixel of the image/frame, and is connected in a 2-D mesh to its 4 nearest neighbors.  This allows arrays of these PE’s to scale very well.  By 1992 Lockheed had GAPP systems with 82,944 elements and by the 2000’s systems were available with nearly 300,000.

In 1998 TeraNex was formed to commercialize this technology, and in 1998 there was a looming problem in television, one that the GAPP, and newly formed TeraNex were well suited to solve.

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March 15th, 2017 ~ by admin

MC6801/6803 Expansion Now Available for the 680x/650x Test System

6801/6803 Expansion Board and PCP

After several months of development an expansion for the 680x/650x Test system is now available to support the very popular and widely used 6801 and 6803 MCUs.  The Motorola 6801 was one of the first (with the 6802) MCU’s that Motorola made based on the MC6800 8-bit processor.  It includes RAM/ROM, Serial I/O and timers.  The test board tests the function of the base CPU, the timers/data capture, and the Serial I/O.  The MC6803 is a 6801 without the built-in ROM and with less I/O.

The expansion supports both types as well as their copies/derivatives made by Hitachi, Fujitsu, SGS and others.  The expansion is included in the complete 680x/650x Test system, bringing its total supported processors to well over 35.  The expansion does require updated firmware, which is included in all new systems (and available to upgrade previously sold systems.)

February 14th, 2017 ~ by admin

Matrox SX-900: x86 Accelerated GPU

Matrox SX-900: Serial# 266 – Nov 1984

In today’s age of GPU’s the GPU is often used to offload the x86 processor.  Many tasks are well suited for the thousands of GPU cores on modern graphics cards, tasks that would be a large burden on an x86 processor.  In 1984 though, Matrox took a different approach to high-end GPU design.  Matrox was founded in Canada in 1976, and has been making graphics cards since they first released the S-100 bus ALT-256 in 1978.  Matrox kept up with the hardware changes of the time, released MULTIBUS boards, Q-Bus boards, and eventually PC compatible cards.

The SX-900 was the value (around $2000) version of their 2 board GXB-1000 (that was $3000-4000).  The Matrox SX-900 was a standard MULTIBUS card with support for 640x480x8bit graphics.  It supported a fill rate of 20 MPixels/sec which was very impressive in 1984.  By comparison, the Nvidia NV1 (STG-2000) released in 1995, was only capable of a 12MPixel/sec fill rate, albeit at a richer color depth.  So how did Matrox, in 1984, achieve such performance?

Matrox SX-900: Powered by a 80286-4 Processor and upD7220 Graphics Primitives Processor

Matrox used an Intel 80286 processor, running at 4MHz (the slowest 286 made) as a Display List Processor.  It handles all high level commands (256+) and then controls the rest of the cards hardware, including the NEC uPD7220 Graphics primitive processor and a advanced pixel processor (implemented in PALs/TTL).  Together they bring rather impressive performance.  The board supports up to 4096 colors (in a Lookup Table) but can only display 16 at a time. Interestingly the board has 512K of 150ns DRAM for use as video memory, more than enough for 640×480 graphics.  Also included is 640 bytes of 25ns ECL SRAM (5x AM9122-25PC), and 16K of 120ns CMOS SRAM implemented with 2 HM6264s.  Firmware (the same firmware used for the GXB-1000) is held in 4 27128 EPROMs for simple updating as needed.

The SX-900 was used in CAD systems, industrial automation, processor control, and other applications where data needed to be shown the user graphically, rather then on a green glowing monochrome text display.  One of the more famous applications was the University of Milan (in Italy) where the SX-900 (supported by Intel iSBC286 computing boards) controlled the K800 Superconducting Cyclotron, a 100MeV particle accelerator.  THis cyclotron ended up being moved and completed at Catania, also in Italy.

Many of these boards are still in use, dutifully displaying graphics and providing user interfaces to thousands of processor control systems in factories and institutions around the world.

January 6th, 2017 ~ by admin

HP 1000 A600: The Lighting Processor

HP A600+ Processor Board. 4x AMD AM2901CDC (1820-3117) 1x AMD AM2904DC and 1x AMD AM2910 (1820-2378). Some versions used 2901’s from National Semiconductor.

In the early 1960’s HP was exploring connecting computers to its various instruments, for control, monitoring, and logging.  The DEC PDP-8 had come out in 1965 as perhaps the first mini-computer and could be used to control HP’s instrument’s.  However, HP determined that it would actually be easier, and faster to design and build their own computers rather than work with DEC.  DEC probably didn’t see HP’s interest as important enough to make it easy (some interfacing for I/O etc would have to be done).  It worked out well for HP however, as this pushed them into an entirely new, and emerging market.

In 1966 HP released the 16-bit HP 2100 (later to be renamed the HP 1000 series).  It was a design that had begun under Union Carbide’s Data Systems Inc, a company HP had recently acquired.  This gave HP a head start, and allowed them to evolve the design to meet their needs (at the time mostly to control instruments).  When released it included not only the hardware but a completely function software suite as well, including a FORTRAN compiler.  They initially ran with a 10MHz clock and a 1.6usec memory cycle time.

Throughout the 1970’s the design evolved, and would lead to many computers.  The 98xx desktop systems using HP’s NMOS BPC Hybrid processor were based on the HP 1000 series.  The design was a fairly simple accumulator based architecture with 2 16-bit accumulators (A and B) and a 15-bit PC and 68-base instructions.  The first version was directly programmed but all subsequent versions were microprogrammed, making alterations and additions to the instruction set much easier, a feature that became important in keeping the HP 1000 around.

The A series were the HP 1000’s of the 1980’s.  Development began around 1980 and the first computers, the A600 and A700, were released in 1982.  These were some of the first LSI based processors for the line.  THe A600 processor was called the ‘Lightning.’  The name “Lightning” came from the Mark Twain quote “Thunder is good, thunder is great, but it is lightning that does all the work.” “Thunder” was a reference to the PDP 11/23, one of DEC’s newer machines at the time.  HP had went from considering using DEC’s computers to run instruments, to the 4th largest maker of such computers in only a decade.  Certainly a fact not lost on either company.

The A600 is an interesting design, it is of course microprogrammed, and is based on AMD AM2901B bit-slice processors, supported by a 2910 microsequencer, and the 2904 status/shift control unit.  The rest of the board is Schottky TTL, PALs, FPLAs. and ROMs.  Each HP 1000 instruction is microcoded into a 56-bit instruction for controlling the 2901’s 2904 and 2910.  These 56-bit instructions directly operation on the processor.  Certain bits interface with certain parts of each chip, so they are directly executed.

A600 – 56-bit microinstruction word directly operates on the hardware (click for LARGE version)

A series of PAL’s contain the microcoding, allowing for easy updating (at the time).  A standard A600 executed 182 standard HP 1000 instructions.  It could do so at a rate of 1 MIPS, with a cycle time of 227 nanoseconds.

Each 2901 is a 4-bit slice processor, and contains 4-bit registers and ALU’s.  The HP 1000 A and B registers are mapped directly to the R0 and R1 registers of the 2901’s and the Program counter resides in R15.  The PAL’s determine what HP 1000 instruction is being executed, and decode it into the proper 2901 assembly code, building the 56-bit instruction word.  This is one of the best examples of how the AMD 2901 (and other bit slicers) were designed to be used.  The end user has no idea, or need to know what is executing their HP 1000 code.  Its is decoded and send to the bit slicers for processing which then return the results to the proper place.  If new functions are needed a new processor does not need to be designed, simply add additional PAL code to decode the new instructions.  And that is exactly what HP did….

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