Intel released the i8755 in 1976, the i8755A in 1977 (with better compatibility with the 8085A and 8086/8). The Intel 8755 is an UV- erasable and electrically reprogrammable ROM (UV-EPROM) and I/O chip. The EPROM portion has 16 384 bits, organized as 2048 words by 8 bits. The I/O portion has two general purpose I/O ports, each I/O port is individually programmable as input or output.  These were essentially a combination of the 8255 PIO and the 2716 EPROM on a single die/package. These were made on a NMOS process.

Intel C8755-8 – 1977

Intel C8755A – 1979

NEC D8755AD -1981

Toshiba TMP8755AC ’83

NEC and Toshiba released similar microcircuits behind Intel. Basically, the microcircuit was intended to work together with the 8085A microprocessor. It differs from its predecessor i8080A in that it has a multiplexed data and lower address bus. The standard three-bus architecture of the microprocessor system is obtained by multiplexing with the help of an additional external register. In this register, the low byte of the address is fixed by the special output signal of the microprocessor.

Intel 87C75PF Engineering Sample – 1988

By 1988, the 8755A was obsolete and Intel released the 87C75 instead (see article on the CMOS 87C75).

Novosibirsk IM1821VM85A – 1989

Around this time, the production of an analogue of the i8755A, the 573RF10 microcircuit, began in the Soviet Union. Why start producing a microchip that the world electronics leader is changing to a more advanced one? The fact is that at the beginning of 1988, the production of IM1821VM85A began in the USSR. This was a radiation hard analogue of the CMOS i80C85A. It was with it that the 573RF10 was supposed to work.

K573RF10E (gold pins) 1990

KM573RF10 – Gold ’92 / tin pins ’93

The chip is made in a 40-pin side-brazed ceramic DIP. Supply voltage +5 V. Programming voltage +21 V. It was produced at the Vostok fab in Novosibirsk on a CMOS process (to match the 80C85A).

Unmarked 573RF10

The 573RF10 is the only CMOS chip in the 573 series.

573RF10 die – single memory cell – radiopicture.listbb.ru

Intel 8755A die – 2 memory cells – cpu-galaxy.at

It is noticeable to the naked eye that the 573RF10 is own Soviet development. The 573RF10 and i8755A dies are completely different. The i8755 has two memory arrays clearly visible, while the 573RF10 has only one.
It must be said that the application of the 573RF10 chip was not wide enough. And in general, the idea did not take root. The next obvious step in evolution was the combination of a microprocessor, ROM and RAM, input-output ports in one chip which was frequently done on the MCS-48 and MCS-51 series MCU’s which were also being produced in the Soviet Union at the time.

Written by guest author Vladimir Yakovlev
Edited/Formatted by John Culver – The CPU Shack Museum
Pictures – The CPU Shack Museum and others

This article is about memory chips manufactured by one of the entities – the leader of the electronic industry of the USSR – Angstrem. As you know, the Soviet Union ceased to exist in December 1991. We restrict ourselves to the development period of the considered memory chips produced at Angstrem, the end of 1991. Let’s make an attempt to track how the capacity of memory chips grew, how technologies were improved that allowed the Soviet Union not to let the world leaders in electronics go far from itself at that time. A small example: Angstrem’s Dynamic RAM 4K went into mass production in mid-1975, Intel introduced its own in 1974. Intel launched a 16K DRAM in 1977, and Angstrem released its counterpart in 1978.

Angstrem Headquarters

Angstrem was established in June 1963 in Zelenograd (outside of Moscow) as a pilot plant in conjunction with the Scientific Research Institute of Precision Technology. At Angstrem, new technologies for the production of microelectronics were developed, and pilot batches of new microcircuits were also produced. The debugged production technology was then transferred to other enterprises of the USSR and countries of Eastern Europe.
The development and manufacture of memory chips was one of the main activities of Angstrem. It was on them that new semiconductor structures and production technologies were more effectively worked out, and the stability of obtaining finished products is considered in world electronics as a sign of technology ownership. It’s relatively easy to make a small batch of good chips, it’s hard to make a process whereby a large amount of chips can be made and be reliable. It was the very low chip yield percentage that played a cruel joke on Angstrem when mastering the production process of the DRAM 565RU7 chip.

SRAM

In 1966, Angstrem created the first MOSFET in the USSR, which was the first step towards the strict goal of creating CMOS integrated circuits. The first CMOS microcircuit, created in the Soviet Union in 1971, was the 16-bit Angstrom matrix of memory cells 1YaM881.The supply voltage is 6 volts instead of 5 volts, like the rest of the chips in this series.

1YaM881 – 1972

The next in a series of static RAM chips was the CMOS K561RU2 (K564RU2), released in 1976. 564 series of chips is a “military” analogue of the 561 series. In these series, there are several dozen microcircuits. The chip has an organization of 256 words by 1 bit.

561RU2 die – 16×16 256bit matrix clearly visible – The image is taken from the site https://radiopicture.listbb.ru/ with the permission of the author.

It contains 2067 integral elements. Supply voltage is 3-15 volts. It’s an analogue of CD4061A.  It should be noted that in most cases ‘analogue’ means similar to, not an exact copy or exactly compatible.  The USSR did make some compatible IC’s, but they mostly made stuff that was similar, but built to their own specifications/needs.

K564RU2A -1978

K561RU2 -1979

The package of the K561RU2 chip is wider than the standard packages of this series.

K565RU2 -1979

The K565RU2 static RAM chip was manufactured using NMOS technology. Chip capacity was 1024 bits (1024×1). Contains 7142 integral elements. An analogue of Intel 2102A, developed in 1974. K565RU2 appeared in 1977. It was originally designed to be placed in a ceramic package, but later, in order to reduce the cost of production, the dies began to be packed in plastic packages.

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When Apple bought P.A. Semi back in 2008 it was the beginning of the era of the iPhone, and their was much speculation as to why Apple was buying a company that made low power high performance PowerPC processors.  Especially since the iPhone ran on ARM and the Mac had moved from PowerPC to x86.

P.A. Semi PA6T-1682M

P.A. Semi was started in 2003 by Daniel Dobberpuhl (who passed away in 2019).  Dobberpuhl was one of the truly greats of microprocessor design, with a career starting at DEC on the T-11 and MicroVAX, before helping DEC transition to the Alpha RISC design (21064).  It was Dobberpuhl who started the design center in Pal Alto (where P.A. Semi would later take its name from) that designed the DEC StrongARM processor.  A processor that was later purchased by Intel and became the XScale line of ARM processors.

After Intel bought the StrongARM line, he then helped start SiByte, making MIPS based RISC CPUs, and continued to do so when SiByte was purchased by Broadcom. So when he started P.A. Semi it was less about PowerPC and more about RISC, PowerPC just happened to be the architecture they chose to use.  The design team had extensive experience on a variety of CPU architectures, including SPARC, Itanium, and the early Opterons.  You can see why this acquisition was so attractive to Apple.

PA6T block diagram

In the few years (2003-2008) from when P.A. was founded to when Apple took them over, they did design, market, and sell a PowerPC processor line called PWRficient based on what they called the PA6T core.  The PA6T-1682M was a Dual core PowerPC processor (the 13xxM was the single core version) with each core running at up to 2GHz with 64K of L1 Instruction cache and 64K of L1 Data cache.  They were fab’d on a 65nm process by TI and ran at 1.1V.  The L2 cache was scalable and shared amongst the cores.  In the 1682M this was a 2M 8-way cache with ECC.  One of the most useful features was their clock stepping.  They could drop to 500MHz at only a few watts per core, and then back up to the full 2GHz in 25us.

AmigaOne X1000 (made by Aeon) PA6T-1682M

The PA6T was only on the marked for a few months (from the end of 2007 to April 2008) before Apple bought them for $300 million, but in this time P.A. Semi had numerous design wins.  Amiga selected it for use in the AmigaOne X1000 computer.  The AmigaOne did not hit market until 2011, which means that while P.A. Semi was bought and completely under control of Apple, they still continued to make, support, and supply their previous customers with the 1682M CPU.  Certainly Amiga wouldn’t be big enough to push Apple to continue making a chip?

They were not, but others were, and the PA6T was such a great processor that it had been selected and designed in to many computer system used by US Defense contractors, and if anyone doesn’t like change, its Defense contractors, so with some prodding by the US Dept of Defense Apple continued to make (or rather have TI make) the PA6T processors.  Curtis-Wright had designed the PA6T into their new CHAMP-AV5 DSP VME64 board, which was used for signals processing across numerous military applications.  They also also used the PA6T (at 1.5GHz) in the VPX3-125 SBC. Themis computers, NEC, Mercury and others designed in the PA6T. Extreme Engineering, another maker of PA6T based boards, referred to the design as ‘ground breaking.’

Extreme Engineering XPedite8070 SBC

It would have been interesting to see what P.A. Semi could have achieved had they not been gobbled up by Apple.  Clearly we see the results of the talent of the P.A. team in what Apple was able to accomplish with their A-series processors, but clearly P.A. had something special for the PowerPC architecture as well.