September 15th, 2013 ~ by admin
Compaq 21364 Alpha Prototype – 2002
The DEC Alpha was one of the fastest processors of the 1990’s. The original 21064, manufactured in CMOS, rivaled the fastest ECL processors and blew away most everything else. Clock speeds were 150-200MHz (eventually hitting 275MHz) at a time when a standard Intel PC was hitting 66MHz, at the very top end. It was manufactured on a 0.75u process using 1.68 million transistors. The Alpha was a 64-bit RISC design, at a time when 16-bit computing was still rather common. This gave the architecture a good chance at success and a long life.
The 21064 was followed by the 21164 in 1995 with speeds up to 333MHz on a 0.5u process, now using 9.3million transistors. It added an on die secondary cache (called the Scache) of 96KB as well as 8KB instruction and Data caches. These accounted for 7.2 million transistors; the processor core itself was only around 2.1 million, a small increase over the 21064. At the time the main competition was the Pentium Pro, the HP PA8800 and the MIPS R10000. Improved versions were made by both DEC and Samsung, increasing clock speeds to 666MHz by 1998.
In 1996 DEC released the next in the series, the 21264. The 21264 dropped the secondary cache from the die, and implemented it off chip (now called a Bcache). The level 1 caches were increased to 64KB each for instruction and data resulting in a transistor count rise to 15.2 million, 9.2 million of which were for the cache, and the branch prediction tables. Frequency eventually reached 1.33GHz on models fab’d by IBM. However the end of the Alpha had already begun. DEC was purchased by Compaq in 1998, in the midst of the development of the enhanced 21264A. Compaq was an Intel customer, and Intel was developing something special to compete with the Alpha.
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September 3rd, 2013 ~ by admin
Arca-1 Rev2 166Mhz Processor – Late 2001
China is generally seen as where devices are made or assembled, rather then where they are designed or invented, certainly in the computer world. In 2001 a Chinese Gov’t funded venture known as ARCA Technologies changed that. ARCA (Advanced RISC Computer Architecture) designed and released a completely new processor known as the Arca-1. At the time there were two design houses working to create China’s first CPU. Arca, and BLX. BLX made the Godson series of processors which are MIPS32 and MIPS64 implementations. Arca, took a different approach. Not only did they seek to make an indigenous design, but they wanted to do so with their own Instruction Set Architecture (ISA).
The ArcaISA is, of course, RISC based, it contains 80 instructions, with each instruction consisting of up to 3 operands, and contains 32 general purpose registers. The original Arca-1 design is made on a 0.25 micron process (by which foundry is unclear, BLX used ST) with a 5-stage pipeline and drawing 1.2W at a clock speed of 166MHz. It contained separate 32 way associative 8K caches for Instruction and Data. The Arca also includes a DSP unit that has a pair of multiply/Accumulate Units (MACs) as well as basic SIMD support for media acceleration (including hardware MPEG2). Not exactly impressive for 2001, but not bad for a first release. However there was more to come.
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April 2nd, 2013 ~ by admin
MC88100 20MHz – 1992
In the late 1980’s Motorola was developing a full 32-bit RISC processor from the ground up. Initially called the 78000, it was renamed the 88000. The first implementation of the 88000 Instruction Set Architecture was the 88100. It included a FPU and integer unit but required a separate chip (the 88200 CMMU) for caching and memory management. Typically 2 of the 88200s were required (one for instruction cache, one for data, 16kb of cache each). A 64lb cache was also available called the 88204. Made on a 1.5u process the 88100 contained 165,000 transistors while the CMMU chips contained 750,000. Each chip dissipated 1.5Watts at 25MHz. Prices in 1989 were $494 for the CPU and $619 each for the CMMUs. A complete system of 3 chips would be nearly $2000. Not exactly competitive pricing.
The initial, and biggest, customers for the 88000 were to be Apple, and Ford Motor Company, an unusual combination to say the least. Apple invested in the 88000 to be the replacement for the 680×0 processors it had been using. Ford was looking to replace the Intel 8061 processors (from which the MCS-96 MCUs were developed) that had run their EEC-IV engine computers since the early 1980’s. Motorola (as well as Toshiba) had been second sourcing these for Ford for sometime. Ford based its choice on the 88100 based ECU on the assumption that Apples adoption of the 88100 would guarantee good software and compiler support. If Apple stuck with it that is..
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January 18th, 2013 ~ by admin
Cypress CY7C601-25GC – First package with heatspreader – Omitted on later versions
In Mid-1987 Sun Microsystems (now owned by Oracle) released the SPARC (Scalable Processor ARChitecture) processor architecture to be used in their computers (replacing the 68k based systems they had previously used). The SPARC was designed from the outset to be an open architecture, allowing manufactures to license and built processors that implemented it using whatever technology they wished. The goal of this was to 1) build a large SPARC ecosystem and 2) keep prices in check by fostering competition among manufacturers. The SPARC is still used today by Oracle, Fujitsu, the European Space Agency and others, owing largely to its design as an open architecture from the very beginning.
The first version was made by Fujitsu on a 20,000 gate array at 1.2 micron and ran at 16.6MHz. In July 1988 Cypress (later to be spun off as Ross and make the famous HyperSPARC line) announced the CY7C601. This was the fastest implementation of the SPARC at the time. It was made on 0.8u CMOS process and contained 165,000 transistors, dissipating around 3.3Watts. As was typical of many processor designs of the time, it was an integer only processor, requiring a separate chip (the CY7C602) for floating point work. In September of 1988, Cypress cross licensed the ‘601 to Texas Intruments in exchange for rights to the 8847 floating point processor. This was mainly to appease one of Cypress main customers who demanded that a second source for the ‘601 chips be available, a demand more common in the 1970s then in 1988 but Cypress obliged. Cyrpress also gained the rights to make the next generation SPARC processor that TI was developing. TI would go on to make many SPARC processors, and continued to be the primary fab for Sun up through the SPARC T2 Plus in 2008. Oracle now used TSMC to fab the T3 and T4 SPARC processors.
January 16th, 2011 ~ by admin
Fairchild developed the Clipper architecture in 1986, and sold it to Intergraph in 1987. The design never enjoyed wide success and was only used in systems made by Integraph, as well as some by ‘High Level Hardware.’ The deign itself was RISC like and competed mainly with the Sun SPARC processors.
The final version was the C400 which was released in 1993 (preceded by the C100 and C300). Presumably there was a C200 but I have not seen any documentation on it. The C400 ran at 50MHz (like the C300) and actually consisted of 3 separate chips. The CPU, the FPU and the CAMMU (Cache/Memory Management Unit). Intergraph developed their own version of UNIX called CLIX to run on the clipper, and demonstrated a version of Windows NT that ran on the C400 as well. Ultimately the lack of software support, and the slow adoption killed the Clipper. While Intergraph was designing the C5, Intel assured them a good supply of processors, and this convinced Intergraph to cancel the C5.
Intergraph C4 MCM
It was also available as a MCM (multi-chip-module) incorporating all three dies in a single ceramic package. This is one of the nicest looking MCMs I have seen, unfortunately the bottom plate was missing when I got it, but the dies are at least visible. I unfortunately am not sure which die is which so if you know, let me know.
February 4th, 2009 ~ by admin
So I bought some chips on eBay, they arrived, and are New Old Stock, made in 2004, really fairly recent. I have a datasheet for them that is marked Winbond which I found rather strange, since the chips, as you can see are marked National. This in itself isn’t super unusual. Occasionally a smaller company will use a larger companies markings to get design wins. The larger company acts in essance like a co-signer, validating and approving of the design.
Winbond isn’t small though, and the datasheet was marked 2006. A quick look on Winbond’s site shows no info on this chip. Turns out Winbond spun off their controller business to a company called Nuvoton. And how did Winbond get the desgin? Yup, National sold off their Super I/O and embedded controller division to Winbond in 2005.
And it is of course a processor, in this case a 16bit RISC processor running at 20MHz based on the (formerly) National CompactRISC architecture.
February 3rd, 2009 ~ by admin
When designing a system, the best performance is often reached by using an ASIC, you can customize it to your design and tweak it for maximum performance. This, however, adds costly development time, and little flexiblility. You could use a general purpose processor; this saves dev time, and cost, but at the expense of performance. What if you could have both? Off the shelf processor technology, AND customizable speed.
You can. This is what Software Configurable Processors are designed for. In simple terms they are a standard CPU core, wrapped in a FPGA. This way istructions for the processort can be configured for maximun speed. If you have a function in your code that is repetitive, it can be reduced to a single instruction for the processor.
One of the leaders in Software Configurable Processors is called Stretch. Their S6000 line of processors use a Tensilica Xtensa core (a VLIW RISC design), wrapped in a custom FPGA. In this way the RISC core can be programmaed on the fly, providing much faster performance then a normal processor, or DSP.
January 26th, 2009 ~ by admin
Automotive computing in manyways is similar to your personal computer, and the same inherent problems. On your PC it is good to have the OS isolated from the normal applications (especially the internet browser). Same thing in your car, you do not want the navigation and media player functions to be able to interfere or crash the control computer. This is why most cars have DOZENS of computers. Renesas has just announced the SH7776, a dual SH-4A cored CPU. One core for the information systems, and one for the control systems. They share a common memory set, but it is segmented to prevent any problems. Each core runs at a whopping 533MHz and can output almost 2000 MIPS.
Clearly thats not enough for Renesas, they through in a graphics core too, a PowerVR core with 3D Rendering.
Source: EEProduct Center