March 29th, 2015 ~ by admin
Chip that come into the museum are all scanned on a Canon 5600F flatbed scanner. It has a good (there is some better though) depth of field, and its fast. Typically chips are scanned at 300dpi, or for small ones (or ones that have a die visible) 600dpi. This keep the file sizes reasonable, yet still allows them to be studied in good detail on CPUShack.com as well our records.
There are on occasion chips that are VERY hard to scan, either the markings are very small, or very shallow. This is becoming common on more modern chips, for one the chips themselves are smaller, and second, they are most often laser marked, and there isn’t enough thickness in the package (or die on some) for the Grand Canyon engraving of the 80’s.
1200 dpi dry scan
This is a Intel QG80331M500 IO Processor made by Intel in 2007. It is the replacement for the 80960 based I/O processors, using instead a 500 MHz XScale ARM Processor core. This scan was done at 1200 dpi, the part number is visible, barely, but the S-spec and FPO (lot code) are not. The markings are laser etched directly onto the surface of the silicon die. This is fairly common on this type of chip (as well as most all of Intel chipsets). How do we improve upon this? Bumping the resolution to 2400dpi just makes a bigger blurry picture (with more noise). What we need is better resolution, at where the scanner works best (less noise at 1200 dpi scan).
Thankfully we can use a ‘technology’ that is very much similar to how modern processors themselves are now made. Dumping water on the scanner, also known as immersion scanning.
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March 17th, 2015 ~ by admin
MCS-4 Test Boards
The MCS-4/40 Test boards are now back in stock and shipping this week. Only have a few available so head on over to the MCS-4 page to order yours.
I also added a PDF of the boards schematic to make interfacing to it easier for any projects you may have in mind.
If you do have a project in mind, or already made one, post about it in the comments, we’d love to see/hear about it.
March 11th, 2015 ~ by admin
Pagetable.com has in interesting post about emulators, specifically one created in 1978 to run Intel 8080 code on a 6502. While emulators today are fairly common, such as running Nintendo (6502) games on a PC, or In Circuit Emulators for development, an 8-bit cross architecture emulator is certainly different. Especially since the 8080 and 6502 were so vastly differing. Certainly a useful tool for teaching oneself a new architecture, and as they were coming out rather rapidly in the 1970’s knowing more then one was a worthy investment.
Todays equivalent perhaps would be emulating a PIC on a 8051. Perhaps someone will give it a try?
March 6th, 2015 ~ by admin
Dawn’s mission: Ceres
Dawn was launched in 2007 by NASA/JPL and was built by Orbital Sciences becoming their first interplanetary spacecraft. Dawns mission was to visit the two largest dwarf planets in the Asteroid belt, Vesta and Ceres. After visiting Vesta for over a year in 2011-2012 Dawn used its ion engines to break orbit, and travel to Ceres, a journey of 2.5 years.
In the next few hours Dawn will be captured by Ceres gravity and begin orbiting it. These protoplanets, are very interesting scientifically as they provide a look into our solar systems past. Dawn will orbit Ceres for several years and perhaps discover what the mysterious bright spots are, among other things. Studying a planet, even a dwarf planet, requires processing power, and for that Dawn is well equipped.
Dawn is solar powered, so power budgets are of great concern. At 3AU (three times further from the sun then Earth) Dawns solar panels are rates at about 1300 Watts. This has to run all the science experiments, the main computers, the comms, and most importantly the electric ion engine, which uses electricity generated from the panels to excite and eject Xenon gas at very high velocities. Thus, power consumption is more important then raw processor power here, especially for the systems that are on most of the time.
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March 1st, 2015 ~ by admin
DEC 78032 DC333R MicroVAX II – 5MHz
DEC’s 32-bit VAX architecture saw many implementations since its introduction in 1977. Early implementations were all multi-chip, but as technology improved the VAX architecture could be implemented (at least partially) on a single VLSI chip. The first implementation on a single chip was the MicroVAX II released in 1985. It contained 125,000 transistors, made on a 3 micron NMOS (DEC proprietary ‘ZMOS’) process and ran at 5MHz (200ns cycle time).
In 1987 DEC released the CVAX, the second generation VAX on VLSI. The CVAX was made on DEC’s first CMOS process, a 2 micron design using 175,000 transistors and clocked from 10-12.5 MHz (80-10ns cycle time). The input clock was a four-phase overlapping clock (so input frequency was 4x the cycle time, or 40-50MHz). Performance was 2.5-3 times better then the MicroVAX II. About half the gain was from process improvement (increased clock speed), while the rest was from architectural changes (mainly pipelining).
DEC DC580C 78034 CVAX+ 16.67MHz
As the CVAX (and its successor the CVAX+) were released the next generation was already being designed by DEC. This was to be Rigel. Rigel has a 6-stage pipeline, and was made on a 2 micron CMOS process and the CPU contained 320,000 transistors, 140k of which were for logic, while the remaining 180k were for memory (cache). The separate FPU chip contained an additional 135,000 transistors. After some early teething pains on the new CMOS process, where yields were almost non-existent, the process finally was refined enough to make commercial samples by late 1988. The target speed for Rigel was a 40ns cycle (25 MHz clock). This would give the Rigel a 6-8x performance gain over CVAX. 2X of this was from the process shrink (and doubling of clock speed) while 3X was from the improved pipelining. The remainder was due to increased memory performance, not the least of which was due to Rigels 2KB of on chip cache.
Rigel, however, had other plans…
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