April 11th, 2018 ~ by admin

PowerPC Processor for TESS Planet Hunter – Updated

TESS Orbiter – Freescale (now NXP) 2010  PowerPC e500

UPDATE: I received a note from a NASA engineer that the final flight DHU was made by SEAKR Engineering rather then Space Micro.  It turns out MIT pursued 2 different DHU systems in the design of TESS.  The Space Micro IPC 7000 was referred to as the DHU and a system by SEAKR (the Athena-3) was selected as the ADHU (Alternate Data Handling Unit).  Apparently MIT wasn’t sure which would be best so essentially characterized both (and most documentation from early on shows the Space Micro system).  In the end however, the SEAKR Athena-3 Single Board computer was selected.

If all goes well, in a few days the NASA TESS (Transiting Exoplanet Survey Satellite) will be launched on a SpaceX Falcon 9 rocket to startits mission to survey a large portion of the sky for possibly Earth-like planets.  TESS’s finds will make great candidates for further study by either Hubble, or JWST (when it finally launches).  While TESS can see transiting planets (the dimming of a star as an exoplanet passes in front of it) it cannot determine much about its composition, or the composition of its atmosphere.  However, having a list of exoplanets to further check out, especially Earth-sized ones, it’s a big help.  TESS was created as part of the NASA Medium Class Explorers Program (MIDEX) which is for mission up to around $200 Million total cost to NASA (not including launch).  TESS itself cost about $75 million (developed in large part by MIT and built by Orbital-ATK on their LEOStar-2 Platform) and the launch services contract was $87 Million with the remainder taken by operations and contingency funding.

Space Micro Proton 400k with Freescale 2020 processor

That makes this one of the least expensive NASA missions, but one that has engendered much more public interest then its cost suggests.  Finding alien worlds captivates people hearts and minds.  So what is at the heart of the TESS orbiter?  Obviously the premier technology is its 4 cameras that will scan the sky, but the computer that powers these is no less interesting.

The 4 cameras are interfaced to a Data Handling Unit (DHU).  Initially the DHU was to be the Space Micro IPC-7000 computer.  The IPC-7000 consists of a TI TMS320C67xx 32-bit DSP and a pair of Xilinx Virtex-7 FPGAS.  They handle all the pre-processing of the imagery collected by the cameras, making it into a format that is easily transmitted back to earth.  The rest of the spacecraft functions (such as actually sending/storing the data and other space craft house-keeping) is handled by a Space Micro Proton 400k SBC.  The Proton 400k is based on a Freescale 2020 1GHz Dual Core PowerPC processor made on a 0.45u process..  Each PowerPC e500v2 core has a 7-stage pipeline with 32K of I-cache and 32K of D-Cache and shares a single 512K L2 Cache.  The computer also containing a pair of 192GB solid state memory boards for buffering imagery data (data is relayed to Earth only once per orbit, so it needs to store data from around 14 days).

Athena-3 SBC – Powered by a 1.067GHz Freescale P2010 Processor

The final flight version of TESS switched to an ADHU made by SEAKR Engineering.  This uses a very similar setup but a bit less powerful processor.  The heart of the ADHU is the Freescale P2010 e500 processor at 1066MHz with 1GB of DDR2 RAM and 1-4GB of Flash.  This is the single core version of the P2020 used in the initial Proton 400k.  The ADHU also includes a RCC5 triple Xilinx Virtex-5 FPGA board to handle additional camera processing functions (and anything else not handled by the P2010 processor).  Solid state storage is a Gen 3 FMC also by SEAKR, containing 3 boards with a total of 192GB of Flash.  The ADHU handled all of the science, processing the raw camera data into useful science data and handling the sending of data to the 100-125MBit/sec Ka-band transmitter.  It also supplies some star reference information used by the MAU (Master Avionics Unit) computer to provide finer attitude control of the satellite.  The MAU is the LeoStar-2 Satellites main computer, and handles all the mechanics of flying the spacecraft outside of the science work done by the ADHU.

Freescale P2020 Processor

In many ways this is a very advanced processor compared to the RAD750 processors we often see on large scale NASA missions.  The Freescale 2020/2010 is not an inherently radiation hardened design, however both Space Micro and SEAKR  implements many radiation mitigating designs in the system design to compensate for this.  It is not as robust as the RAD750 but it is a $75 million earth satellite with a target mission life of 2-years so it doesn’t need to be. The 2020 processor does give TESS tremendous processing power for a scientific satellite, allowing for a lot of pre-processing of the imagery.  This allows TESS to handle much of the grunt work, and send scientists here on Earth only the very best data, in a format that is the most useful to them.


April 9th, 2015 ~ by admin

The e2v PowerPC and HiTCE Packages

Atmel PC7410MGH450LE - Motorola Marked Package

Atmel PC7410MGH450LE – Motorola Marked Package – 2003

In the 1970’s second sources were quite important in the processor industry.  They provided a stable supply of a designed in part if the primary manufacturer (which often only had a fab or 2) had problems.  They also could widen the market for the processor.  Many of these agreements were kept active for decades after, resulting in some interesting results.

Motorola licensed many of their design to SGS, which later merged with Thomson to become STMicroelectronics. though the Thomson name was still used.  Thomson license built most of Motorola’s product line, as well as many high reliability versions.  In 1999 Atmel bought Thomson-CSF Semiconductors, and continued to make Motorola products (in their Grenoble France fab), which now included Motorola’s PowerPC line as well as the 68k line of processors.  This portion of Atmel was sold to e2v (in England) in 2006, which continued to produce the Motorola (now spun off as Freescale) PowerPC line, now branded as e2V.

The packaging used by e2v (and previously Atmel) is the same as that used by Motorola/Freescale.  The packages were custom made for Motorola/Freescale by Kyocera (and others) and so often chips with both Atmel/Motorola and e2v/Freescale markings can be found.  It is this packaging that is of interest, as it shows an interesting aspect of processor design.

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April 29th, 2014 ~ by admin

CPU of the Day: Xionics XipChip1

Xionics XipChip1

Xionics XipChip1

It was the late 90s and high integration was the name of the game. Xionics (based in Burlington, Mass) and IBM set out to create an intelligent peripheral controller meant to replace logic/ASICs in printers, copiers, and other imaging products with something more useful.  Xionics was originally founded in 1978 in the U.K.  and in the 1980s began making document imaging products.

The XipChip1 is what they came up with. It is a PowerPC 401 core, running at 40MHz with 2KB I Cache + 1KB D Cache made on a 0.36u 4-Layer CMOS process at IBMs plant in Bromont Canada. They included a JPEG engine, DMA controller, Raster Graphics Engine, and a 240MHz RAMBUS controller (hey it was the 90s, RAMBUS was all the rage).  Xionics sold their technology to a number of printer companies (Ricoh, Panasonic, Xerox, HP and many others) and their software was widely adopted. By 1999 Xionics was bought out by Oak Technology which was acquired by Zoran in 2003.

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CPU of the Day

July 26th, 2013 ~ by admin

Apple G3 Prototype: The Goleta and IBM Arthur Processor

IBM Arthur Processor - 1997

IBM Arthur Processor – 1997

By 1997 the PowerPC 604e was getting a bit dated.  Apple needed an updated faster processor for their new computers and IBM and Motorola needed a new processor to sell to Apple.  The PowerPC 750 was an evolution of the 604e and became the core of Apple’s various G3 systems.

In early 1997 Apple , IBM, and Motorola (together known as the AIM Alliance) were working on what would become the PowerPC 750.  It’s code name? The Arthur.  Apparently someone at IBM or Motorola had a liking for Sherlock Holmes as the 745 was codenamed Conan and the 755 Doyle, after Sir Arthur Conan Doyle, writer of Sherlock Holmes.  This particular part is date coded R20003PAP which means it was made in mid-May of 1997, 6 months before the G3 and PowerPC 750 were officially released.

The card the Arthur processor (hand labeled 300Mhz) resides on is an Apple Prototype known as the Goleta.  The Goleta was one of the first Apple G3 products.   It was to be used in the PowerMac 9700 aka the PowerExpress which was to be a 6 slot G3 PowerMac running at 275MHz.

Apple Goleta G3 Prototype

Apple Goleta G3 Prototype – Click here to see the full card.

It never made it past the prototype stage.  The card is labeled as serial #014 making it a very early prototype, though how many total were made is not known.  The card may have been used at Apple for testing other deigns as well and certainly was a test bench for the new 750 PowerPC Processor.  This was a chaotic time for Apple as they were struggling to pull out of near bankruptcy.  Steve Jobs had only just returned to the company and radically changed what Apple was doing, and what they were not doing (making money).

February 17th, 2013 ~ by admin

IBM Blue Gene/Q: The Heart of a Supercomputer

Usually we find vintage processors here at the CPU Shack Museum, however, from time to time, we get our hands on something very new, and usually significant.  If by significant one means the processor from a Top500 supercomputer then yes, it is significant.


IBM 51Y7638 – Produced Early 2012 – Blue Gene/Q 1.6GHz 18 Core PowerPC-A2

This is a Compute card from an IBM Blue Gene/Q (specifically the 6 rack BG/Q running at England’s Science & Technology Facilities Council Daresbury Lab in Cheshire).  A Blue Gene/Q system is made up of these cards, 32 per ‘Node Card’, and 1024 per rack. This doesn’t count the I/O board which use a similar design and contains 8 Compute cards per rack.

BlueGeneQ ASIC die shot

BlueGeneQ ASIC die shot

Each of the Compute cards contains a large ASIC (the large chip in the middle).  This ASIC contains 18 PowerPC-A2 processor cores running at 1.6GHz.  16 of them are ‘User’ cores, 1 is for system management (handles interrupts  message passing, etc) and the 18th is a spare, for increased fault tolerance. The ASIC also contains 32MB of shared L2 cache and a dual 1.3GHz memory controller for the 16GB of DDR3 memory on the card.   All said this 45nm chip contains 1.47 Billion transistors, but only dissipates 55Watts, granted, that adds up when you have thousands of them.

A ‘basic’ system contains 4 racks, so 4096 compute cards (4128 if you count the the I/O boards). Together this is 65,536 user cores and consumes upwards of 85kW of power (this actually makes it one of the most efficient super computers available).

So how do these cards become available?  Simply put when you have so many in a system, statistically you are going to have failures, and somewhat frequently.  IBMs target failure rate, based on a 96 rack system (which is massive) is 70 hours.  That’s one failure  every 3 days.  At this point the common reaction is to express shock at the dismal reliability of such a system, however, lets put it another way, that’s one failure out of 98,000+ Compute cards (yes there are other failure points but for the sake of argument we’re using just the compute cards).  If you run an IT department that services nearly 100,000 computers and you only have to fix something twice a week, there is a good chance you should get a raise.


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CPU of the Day

April 12th, 2009 ~ by admin

Keeping your code safe: Secure Processors

Performing your banking with an unsecured connection, or surfing the web without a anti-virus is dangerous to say the best. Your data may become compromised which of course could serious ruin your day.  These problems extend to the hardware level as well.  In such things as your microwave, their is software running on the hardware to control it.  It would be possible to extract this software code given the right tools.  Stealing kitchen appliance code is not a particular threat obviously. However, there ARE applications where the software running on a set of hardware IS very important, more so often then the hardware itself.  Take for example the battlefield management software on a tank, or the flight control system on a F-22A Raptor.  This is not something you want someone to be able to recover.

Dallas Maxim DS2252T-128-16

Dallas Maxim DS2252T-128-16

Several companies make what are called ‘Secure Processors.’ These are processors designed to keep the code on them VERY secure.  Above is one from Maxim, tamper with it, and the SRAM is auto erased to all 0’s rendering the code useless.  It has encrypted data buses, on-board AES encryption, random key generators, the works.

CPU Technology CPU872 Acalis

CPU Technology CPU872 Acalis

A Company called CPU Tech has a processor called the CPU872, which is now available for commercial use (previous designs have been DoD only). Programs are securely booted from encrypted flash and decrypted onto on-chip embedded DRAM, and neither cleartext nor the decryption key is ever accessible, according to CPU Tech. In a multi-processor system, all I/O communication between CPU872 devices is also secured, according to the firm.  This processor includes 8MB of onboard DRAM, as well as a pair of 800MHz PowerPC 440 cores.  The security however doesn’t start at the chip; CPU Tech only uses ‘Trusted Foundaries’ in the manufacture of their parts, to ensure malicious hardware is not added to the part during fabbing.

April 1st, 2009 ~ by admin

Freescale Releases new 6-core Comm. Processors

Freescale is beginning to turn out new embedded processors on a 45nm process. The same process size Intel uses to make the Corei7 CPU’s Freescale is using to make 6 PowerPC cored devices for the communications market.  With speeds of up to 1.3GHz at only a few watts the performance is rather good.

The target market is 3G and 4G cellular base stations.

Source: EE Times

February 16th, 2009 ~ by admin

Modern CPU Flops: Itanic, PowerPC, and Puma

CNet Blog nanotech recently did an article about the 3 most recent CPU design flops by Intel, IBM, and AMD.

For Intel they chose the Itanium, and Itanium 2, there is no doubt that the Itanic as it is commonly called was a failure of epic proportions. It cost to much, and ad NO decent backwards compatibility and no existing code base.  Intel of course still keeps plugging away on it.

For AMD editor Brooke chose the Puma, AMD’s much hyped and highly underperforming CPU/GPU, no argument here, it was and is a dog.

Where I disagree is the selection of the PowerPC by IBM.  While Apple’s use of the PowerPC (all 10 years of it) ultimately ended in failure, the PowerPC did find its niche in many industries.  Servers and supercomputers worldwide use thousands of PowerPC CPU’s.  IBM has created many embedded versions which are used in everything from industrial control to running printers.  IBM has also successfully license the PowerPC architecture to many other companies (over 20 at that, including a couple CPU’s running on Mars). Xilinx makes FPGA’s with multiple integrated PowerPC cores which find there way into about everything. Apple continues to be involved in PowerPC through their purchase of PA Semiconductor.

Perhaps the most well known users of the PowerPC today? The Nintendo Wii and the XBOX 360.