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EMBEDDED: MOTOROLA STREAMLINES 68K FOR THE BEST OF BOTH WORLDS (October 21st 1994) Motorola Semiconductor Group's High Performance Embedded Systems Division used the Microprocessor Forum to outline a new embedded microprocessor RISC architecture called ACE (and previously code named ColdFire). ACE uses a streamlined 68000 instruction set to produce a 32-bit RISC architecture where instructions only take a cycle to execute. Compared to the 68k instruction set, ACE removes instructions used primarily by desktop applications and reduces support for read-modify-write operations. A few new instructions were added too, mainly cadged from the 68020. To give a comparison of how this effects code in practice, Motorola says that if you take some printer code and run it through a 68040 compiler, around 7% of the resulting binary will consist of instructions not supported in ACE. ACE instructions themselves are still of variable length with operations defined by 1, 2 or 3 16-bit words. As such, the new architecture supports development tools already targeted for its embedded M680x0 lines.
The chip consists of a two-stage instruction fetch pipeline, a two-stage operand execution pipeline and a first in, first out instruction buffer to decouple the two pipelines. The company says that using a variable-length RISC instruction set allows it to achieve significant code density advantages over conventional fixed-length RISC processors that restrict machine language instructions to the same size. Each fixed-length instruction has a minimum length (typically 32 bits), so simple instructions take up as much memory space as advanced instructions, resulting in higher memory requirements and larger compiled code, it says. ACE's variable-length design, which supports instructions of different lengths, allows code to be packed more efficiently in memory it claims. Product is due next year.