SUN DISCLOSES ULTRASPARC-II;
SPARC CHARGES TO 420 SPECINT AND 660 SPECFP

SAN JOSE, Calif. -- October 11, 1995 -- Today at the Microprocessor
Forum, Sun Microsystems' SPARC Technology Business disclosed its
second-generation UltraSPARC-II high-performance RISC (Reduced
Instruction Set Computing) microprocessor.

UltraSPARC-II features the Visual Instruction Set (VIS instruction set)
and scales New-Media processing and data bandwidth to industry highs of
3 giga-operations/second (GOPs) and 4.8 gigabyte/second (GByte/s). At
250 to 300 MHz, UltraSPARC-II will deliver an estimated 350 to 420
SPEC92int and 550 to 660 SPEC92fp (2 megabyte cache). Device sampling
and production are scheduled for the first and second half of 1996,
respectively.

"The UltraSPARC program is about year-after-year, systematic and
aggressive performance delivery," stated Anant Agrawal, vice president
of SPARC Technology Business Engineering. "UltraSPARC-I is in
production today, and we're demonstrating 200 MHz devices. In 1996,
UltraSPARC-II raises our clock speed, adds in additional performance
features and ultimately further scales our processing performance by 50
percent. And, we'll take this one step further-UltraSPARC-III promises
1000 SPEC92int and 1500 SPEC92fp."

Agrawal continued," UltraSPARC-I delivers the New-Media processing and
data bandwidth requirements of today's and tomorrow's networked
environments. UltraSPARC-II builds upon this foundation by scaling the
Visual Instruction Set to 3 billion operations per second and data
bandwidth to 1.6 GByte/s."

The 5.4 million transistor UltraSPARC-II is the second-generation of the
UltraSPARC microprocessor family. It features integrated New-Media
support for desktop videoconferencing, real-time MPEG-2 decode, video
effects and texture-mapped triangle rendering. Its highly scalar and
high-data-throughput design enables UltraSPARC-II to move data at a peak
rate of 1.6 GBytes/second and, while employing the New-Media Visual
Instruction Set (VIS), it can operate at a rate of 3 GOPs (300 MHz).
UltraSPARC-II will be manufactured by Texas Instruments, Inc. (TI) at
its advanced CMOS fabrication facility in Dallas, Texas using TI's
advanced EPIC4, 0.35 micron, 2.5 volt, five-layer metal CMOS process.

UltraSPARC-II has a clock range of 250 to 300 MHz, with an estimated 350
to 420 SPEC92int and 550 to 660 SPEC92fp. Microarchitectural enhancements
have been made to UltraSPARC-II for reduced instruction cycle time
including the addition of full software prefetch and the ability to handle
multiple outstanding requests. Second-level cache support has also been
extended to 16 MBytes and UltraSPARC-II features flexible system clocking
and cache interface schemes.

SPARC Technology Business, a division of Sun Microsystems, Inc., was
formed in April 1993 to develop, design and distribute SPARC technologies
and products worldwide. The division's portfolio includes microprocessors,
chipsets, modules, boards, technology licenses, silicon and systems
packages and consulting services. Currently, the division has more than
500 employees working in product development, engineering, marketing and
worldwide sales and support. Complete information on SPARC Technology
Business is available via the World Wide Web at http://www.sun.com/stb.
Information on the SPARC architecture, including a complete list of its
supporters is available at http://www.sparc.com.