MORE POWERPC 630 DETAILS REVEALED; AS/400 EARLY VERSION NEXT YEAR (October 7th 1994) Next year IBM will launch a high-end AS/400 containing a multi-chip implementation of the PowerPC '630' (nee POWER3) processor. According to Frank Soltis, chief architect of the AS/400, the aim is to get the 630 onto a single chip during 1996. In the meantime, IBM's Rochester, Illinois facility has designed its own multi-chip variant: "We wanted the 630 architecture and could not wait for the single chip", he said.
Rochester's proto-630 implementation uses seven chips. All the execution units together with an instruction cache are bundled onto the first. The floating point unit gets chip two to itself, while chips three, four, five and six provide 256kBytes of data cache. The final part handles I/O. Details of exactly how many execution units are present were not to hand, but Soltis says that the multi-chip implementation can dispatch four instructions per cycle and up to 13 instructions can be executing concurrently. This disparity between maximum number of instructions dispatched and maximum executing sounds a little odd, but if right, this will be a very highly scaled processor which should be virtually stall-proof.
In order to compensate for the comparatively sluggish inter-chip connections, the AS/400 unit is fabricating the multi-chip module in BiCMOS. However the "proper" single chip 630 will be fabricated in the cheaper & slower CMOS like the rest of the PowerPC family. Soltis says that the multi-chip part is currently sampling and running in the labs at 200MHz. Initially, it will be driven at a lower clock-speed, giving IBM some headroom for performance expansion - expect next year's AS/400s to run at something like 150MHz or 166MHz. Whether the finished 630 will actually squeeze down onto a single chip is still a moot point. There is a possibility that it will end up with the cache on a separate piece of silicon to the rest of the processing units.
In a departure from the PowerPC norm, the 630 contains extra instructions, requested by IBM's RS/6000 and AS/400 divisions. So, according to Soltis, it contains special hooks for interfacing with matrix-manipulation processors, as requested by the RS/6000 division. Meanwhile the AS/400 developers asked for, and got, special memory-addressing modes, string manipulation and decimal arithmetic. Historically, the PowerPC 630 started life as the POWER3 architecture, and was subsequently handed over to the Somerset joint design lab.
The inclusion of IBM-specific (and possibly undocumented) instructions into the 630 looks a little strange in the context of promoting PowerPC as a vendor-neutral processor standard. Indeed, Soltis admits that Motorola is currently muttering that it doesn't really want matrix-manipulation hooks and the like. However, he says that the extra functions take up very little extra silicon real estate and that by the time the chip comes out, Motorola and Apple might be grateful for the extra facilities.