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January 2nd, 2020 ~ by admin

Chips in Space: Making MILSTAR

Milstar Satellite

Back in the late 1970’s having a survivable space based strategic communications network became a priority for the US Military.  Several ideas were proposed, with many lofty goals for capabilities that at the time were not technologically feasible.  By 1983 the program had been narrowed to a highly survivable network of 10 satellites that could provide LDR (Low Data Rate) strategic communications in a wartime environment.  The program became known as MILSTAR (Military, Strategic, Tactical and Relay) and in 1983 President Reagan declared it a National Priority, meaning it would enjoy a fair amount of freedom in funding, lots and lots of funding.  RCA Astro Electronics was the prime contractor for the Milstar program, but during the development process was sold to GE Aerospace, then Martin Marietta, which became Lockheed Martin before the 3rd satellite was launched.  The first satellite was suppose to be ready for launch in 1987, but changing requirements delayed that by 7 years.

Milstar Program 5400 series TTL dies

The first satellite was delivered in 1993 and launched in February of 1994.  A second was launched in 1995 and these became Milstar-1. A third launch failed, which would have carried a hybrid satellite that added a Medium Data Rate (MDR system).  Three Block II satellites were launched in 2001-2003 which included the MDR system, bringing the constellation up to 5.  This provided 24/7 coverage between the 65 degree N/S latitudes, leaving the poles uncovered.

TI 54ALS161A

The LDR payload was subcontracted to TRW (which became Northrup Grumman) and consisted of 192 channels capable of data rates of a blazing 75 – 2400 baud.  These were designed for sending tasking orders to various strategic Air Force assets, nothing high bandwidth, even so many such orders could take several minutes to send.  Each satellite also had two 60GHz cross links, used to communicate with the other Milstar sats in the constellation.  The LDR (and later MDR) payloads were frequency hopping spread spectrum radio system with jam resistant technology.  The later MDR system was able to detect and effectively null jamming attempts.

The LDR system was built out of 630 LSI circuits, most of which were contained in hybrid multi layer MCM packages.  These LSIs were a mix of custom designs by TRW and off the shelf TTL parts.  Most of the TTL parts were sourced from TI and were ALS family devices (Advanced Low Power Schottky), the fastest/lowest power available.  TI began supplying such TTL (as bare dies for integration into MCMs) in the mid-1980’s.  These dies had to be of the highest quality, and traceable to the exact slice of the

Traceability Markings

exact wafer they came from. They were supplied in trays, marked with the date, diffusion run (a serial number for the process and wafer that made them) and the slice of that wafer, then stamped with the name/ID of the TI quality control person who verified them.

These TTL circuits are relatively simple the ones pictures are:
54ALS574A Octal D Edge Triggered Flip flop (used as a buffer usually)
54ALS193 Synchronous 4-Bit Up/Down Binary Counters With Dual Clock
54ALS161A Asynchronous 4-Bit Binary Counters


Looking at the dies of these small TTL circuits is quite interesting.  The 54ALS161A marking on the die appears to be on top of the a ‘160A marking.  TI didn’t make a mistake here, its just that the the 160 and 161 are essentially the same device.  The 161 is a binary counter, while the 160 was configured as a decade counter.  This only required one mask layer change to make it either one.

ALS573 and ALS574 die

Similarly with the 54ALS574, which shares a die with the more basic ‘573 D type transparent Latch.  This was pretty common with TTL (if you look at a list of the different 7400 series TTL you will notice many are very similar with but a minor change between two chips).  It is of course the same with CPUs, with one die being able to be used for multiple core counts, PCI0E lanes, cache sizes etc.

Together with others they perform all the function of a high reliability communications systems, so failure was not an option.  TI supplied thousands upon thousands of dies for characterization and testing.  The satellites were designed for a 10 year lifetime (it was hoped by them

Milstar Hybrid MCM Command Decoder (picture courtesy of The Smithsonian)

something better would be ready, no doubt creating another nice contract, but alas, as many things are, a follow on didn’t come along until just recently (the AEHF satellites).  This left the Milstar constellation to perform a critical role well past its design life, which it did and continues to do.  Even the original Milstar 1 satellite, launched in 1994 with 54ALS series TTL from the 1980s is still working, 25 years later, a testament to TRW and RCA Astro’s design.  Perhaps the only thing that will limit them will be the available fuel for their on-orbit Attitude Control Systems.

While not necessarily a CPU in itself these little dies worked together to get the job down.  I never could find any of the actual design, but it wouldn’t surprise me if the satellites ran AMD 2901 based systems, common at the time or a custom design based on ‘181 series 4-bit ALUs.  finding bare dies is always interesting, to be able to see into whats inside a computer chip, but to find ones that were made for a very specific purpose is even more interesting.  The Milstar Program cost around $22 Billion over its life time, so one must wonder how much each of these dies cost TRW, or the US Taxpayer?

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CPU of the Day

December 19th, 2017 ~ by admin

Chip of the Day: TRW MPY-16AJ – Making Multiplication Manageable

TRW MPY16AJ – 1978

In Primary School students are tasked with memorizing their multiplication tables.  Taking the time to manually calculate 6×5 is much slower than simply committing the result to memory.  This allows more complex math to be processed quicker as the students skills develop.  Typically this is limited to numbers up to 12×12, resulting in 144 results to ‘store.’  In computing the same can be done.  A ROM can be used as a lookup table for multiplication.  The problem is it does not scale well.  Handling 4×4-bit multiplication requires a 256×8 ROM (2m+n addresses and m+n outputs). This could be handled by a many ROMs available in the 1970’s.  Anything more than 4-bits though was simply not possible.  This gave rise to the need for multipliers to calculate the result.

TRW MPY16AJ – Large Heatsink affixed to package to dissipate its 5W

This was a problem TRW set out to rectify in 1976.  TRW LSI Products was formed in the 1960’s to commercialize the transistor products that had been developed by Pacific Semiconductors, a division of TRW.  It was James Buie who invented the TTL logic gate in 1961 while working for TRW.  TTL went on to become the logic standard throughout the 1970’s and 80’s.   TRW was involved in aerospace, helping design planes, satellites, and missiles, fields that required processing of signals data, what became known as Digital Signal Processing (DSP).  In the 1980’s processors were designed to handle this, such as the TI TMS320 series, but in the 1970’s it had to be done with discrete components.  DSP systems had several needed blocks, Fast ADCs, ALUs, and multipliers.  TRW invented fast ADCs to handle the inputs, and ALUs were available such as AMDs Am2901 or even the TTL series 74181s.  Multipliers however were not widely available, especially for large bit-widths.

MPY-16 die

TRW’s first multiplier was a custom device to work with their own avionics processing system.  It was made on a Bipolar process, and multiplexed the entire product, using around 40 pins total (the entire product was multiplexed with the operands).  It could handle a multiply in 330ns worst case.  Interestingly yields of the device were considered ‘excellent’ at 3 working devices per wafer (out of 19 per wafer (most likely a 2″ wafer)).  Today, yields like that would be completely unacceptable.

TRW designed the MPY-16AJ as a brute-force 16×16 multiplier.  It was designed on a Bipolar process with around 3600 gates.  It implements a series of AND gates and CARRY-SAVE-ADDERS to implement the multiplication.  There are faster methods, but they come at the cost of complexity and power draw.  As designed the the MPY-16AJ dissipates 5 Watts while handling a signed (2’s complement) multiplication in a worse case 230ns).  They MPY16 was packaged in a large 64-pin package to limit the # of pins that had to be multiplexed.  The lower 16-bits of the product are multiplexed with one of the operands.  This is acceptable as in many applications the upper 16-bits of the product are sufficient accuracy.  The 64-pin package allowed for not less multiplexing, but also a much larger surface for heat dissipation.  A heatsink was also affixed to the package as well.

Micron (Russia) 1802VR5 – MPY16HJ Clone made in 1992

Later versions of the MPY-16 added support for unsigned multiplication as well (the MPY16H) and became the standard for 16-bit multipliers.  Compatible multipliers were made by Analog Devices (ADSP1016, 40-50ns at 150mW) and LOGIC LMU16/216) in CMOS, by Weitek (WTL1516/A/B, 50-100ns at 0.9-1.8W) in NMOS, by Synertek (SY66016 100ns at 1.5W) in HMOS, by AMD (Am29516 38ns at 4W) in ECL, as well as many others.  These were implemented internally with different processes, and different multiplier algorithms but externally they all mimicked the standard TRW MPY16J and served as the basis of many signal processing and high end math computers.  As a testament to their usefulness, the MPY16 was also copied by the USSR as the 1802VR5.  The TRW MPY16 was last made in the mid-1980’s but its clones continued to be made into the 1990’s.  Today its functions can be handled by any DSP, CPU or even coded into a FPGA, but for a time, the MPY16 multiplied the efficiency of many processing systems.