desyrel ile ilgili yorumlar percocet mixed with lunesta vicodin lunesta together ambien vs lunesta price
February 3rd, 2016 ~ by admin

The End of the Omega

ST STi5500 - The Original 50MHz Transputer based Omega

ST STi5500 – The Original 50MHz Transputer based Omega

In January ST announced that they would be exiting the Digital Set Top Box (STB) market.  This is a market that they arguably led for the last 20 years, and one that really began with their Omega processor in 1997. The ST Omega processor line, beginning with the STi5500 powered set top boxes, for cable companies, satellite companies, and DVR’s as well as other TV connected devices.  Open up a satellite TV receiver from the last 20 years and you are very likely to find a STi Omega chipset.

The STi5500 was the beginning, and interestingly at its core was a ST20 processor, based on the Inmos Transputer (which ST now owned) from the late 1980’s.  The Transputer was meant to revolutionize computing, making processors so cheap, that they could be embedded into pretty much any other logic device, what today we call an SoC, but in 1985, was a novel idea.  At the time it didn’t really succeed, but ended up seeing its intended use 10+ years later in the Omega.  In the 1980s the Transputer saw speeds of up to 30MHz, int he STi5500 it ran at 50MHz with 2K of I-cache + 2K of Data Cache as well as 2K of SRAM that could be used as data cache.

ST STi5514 - Enhanced 180MHz Omega

ST STi5514 – Enhanced 180MHz Omega

In the early 2000s the Omega was upgraded to a faster ST20 core, eventually hitting 243MHz in the STi5100, now with the caches increased to 8K each, as well as 8K of SRAM.  This was getting to be the limit of the ST20 Transputer core.  ST needed a core that could support higher speeds running such things as Java and Windows CE amongst other things, as well as support the higher resolutions and audio quality requirements.

ST handled this is in two entirely different ways.  First they licensed the SH-4 32-bit RISC core from Hitachi, a rather surprising move but STBs was not a market Hitachi was in, so it was in both companies best interest.  ST also was working on their own new core to replace the ST20, and they had help, from a very surprising partner.

Read More »

November 1st, 2013 ~ by admin

nCube and the Rise of the HyperCubes

nCube/2 Processor - 20MHz The logo is a tesseract - 4-way Hypercube

nCube/2 Processor – 20MHz
The logo is a Tesseract – a 4-way Hypercube

In 1983 Stephen Colley, Dave Jurasek, John Palmer and 3 others from Intel’s Systems Group left Intel, frustrated by Intel’s seeming reluctance to enter the then emerging parallel computing market.  They founded a company in Beaverton, Oregon known as nCube with the goal of producing MIMD (Multiple Instruction Multiple Data) parallel computers.  In 1985 they released their first computer, known as the nCube/10.  The nCube/10 was built using a custom 32-bit CMOS processor containing 160,000 transistors and running initially at 8MHz (later increased to 10).  IEEE754 64-bit floating point support  (including hardware sqrt) was included on chip.  Each processor was on a module with its own 128KB of ECC DRAM memory (implemented as 6 64k x 4 bit DRAMs.)  A full system, with 1024 processor nodes, had 128MB of usable memory (160MB of  DRAM counting those used for ECC).  From the outset the nCube systems were designed for reliability, with MTBFs of full systems running in the 6 month range, extremely good at the time.

The nCube/10 system was organized in a Hypercube geometry, with the 10 signifying its ability to scale to a 10-way Hypercube, also known as a dekeract.  This architecture allows for any processor to be a maximum of 10-hops from any other processor.  The benefits are greatly reduced latency in cross processor communication.  The downside is that expansion is restricted to powers of 2 (64, 128, 256, 512 etc) making upgrade costs a bit expensive as the size scaled up.  Each processor contained 22 DMA channels, with a pair being reserved for I/O to the host processor and the remaining 20 (10 in + 10 out) used for interprocessor communication.  This focus on a general purpose CPU with built in networking support is very similar to the Inmos Transputer, which at the time, was making similar inroads in the European market.  System management was run by similar nCube processors on Graphics, Disk, and I/O cards.  Programming was via Fortran 77 and later C/C++. At the time it was one of the fastest computers on the planet, even challenging the almighty Cray.  And it was about to get faster.

Read More »