The CPU Shack Museum CPU History Museum for Intel CPUs, AMD Processor, Cyrix Microprocessors, Microcontrollers and more. Sun, 09 Aug 2020 22:57:43 +0000 en-US hourly 1 The Forgotten Ones: HP Nanoprocessor Sun, 09 Aug 2020 22:18:31 +0000

Original Nanoprocessor prototypes from 1974-75. Note hand written wafer number, open die cover and early part number (94332)

Back in the 1970’s the Loveland Instrument Division (LID) of HP in Colorado, USA was the forefront of much of HP’s computing innovation.  HP was a leader, and often THE leader in computerized instrumentation in the early 1970’s.  From things like calculators, to O-scopes to desktop computers like the 9825 and 9845 series.  HP made their own processors for most all of these products.  The early computers were based on the 16-bit Hybrid processor we talked about before.  At around the same time, in 1974, the HP LID realized they needed another processor, a control oriented processor that was programmable, and could be used to control the various hardware systems they were building.  This didn’t need to be a beast like the 16-bit Hybrids, but something simpler, inexpensive, and very fast, it would interface and control things like HPIB cards, printers, and the like.  The task of designing such a processor fell to Larry Bower.

The result was a Control Oriented Processor called the HP nanoprocessor.  Internally it was given the identifier 94332 (or 9-4332), not the most elegant name, but its what was on the original prototypes and die.   The goal was to use HP’s original 7-micron NMOS process (rather then the new 5-micron NMOS-II process) to help save costs and get it into production quickly.

Nanoprocessor Features – Note the speed has been ‘adjusted’


The original design goal was a 5MHz clock rate and instructions that would execute in 2 cycles (400ns).  The early datasheets have this crossed out and replaced with 4MHz and 500ns, yields at 5MHz must not have been high enough, and 4MHz was plenty.

Handwritten Block diagram


The Nanoprocessor is interesting as it is specifically NOT an arithmetic oriented processor, in fact, it doesn’t even support arithmetic.  It has 42 8-bit instructions, centered around control logic.  These are supported by 16 8-bit registers, an 8-bit Accumulator and an 11-bit Program Counter.  Interface to the external world is via an 11-bit address bus, 8-bit Data bus and a 7-bit ‘Direct Control’ bus which functions as an I/O bus.  The nanoprocessor supports both external vectored interrupts and subroutines.  The instructions support the ability to test, set and clear each bit in the accumulator, as well as comparisons, increments/decrements (both binary and BCD), and complements.

Here is one mask (Mask 5 of 6) for the prototype Nanoprocessor. You can see its simplicity.  On the bottom of the mask you can see the 11-bit address buffers and Program Counter

2.66MHz 1820-1691 – note the -5V Bias Voltage marked on it

The Nanoprocessor required a simple TTL clock, and 3 power supplies, a +12 and +5VDC for the logic and a -2VDC to -5VDC back gate bias voltage.  This bias voltage was dependent on manufacturing variables so was not always the same chip to chip (the goal would be -5VDC).  Each chip was tested the and voltage was hand written on the chip.  The voltage was then set by a single resistor on the PCB.  Swapping out a Nanoprocessor meant you needed to make sure this bias voltage was set correctly.

If you needed support for an ALU you could add one externally (likely with a pair of ‘181 series TTL).  Even with an external ALU the Nanoprocessor was very fast.   The projected cost of a Nanoprocessor in 1974 was $15 (or $22 with an ALU),  In late 1975 this was $18 for the 4MHz version  (1820-1692) and $13 for the slower 2.66MHz version (1820-1691).

At the time of its development in 1974-1975 the Motorola 6800 had just been announced. The 6800 was an 8-bit processor as well, made on a NMOS process, and had a maximum clock rate of 1MHz.  The initial cost of the 6800 was $360, dropping to $175, then $69 with the release of the 6502 from MOS.  By 1976 the 6800 was only $36, but this is still double what a Nanoprocessor cost


An early ‘slide deck’ (the paper version equivalent) from December 1974 sets out the What Why and How of the Nanoprocessor.  The total cost of its development was projected to be only $250,000 (around $1 million in 2020 USD).  The paper compares the performance of the Nanoprocessor to that of the 6800.  The comparisons are pretty amazing.

Interrupted Count Benchmark

For control processing interrupt response time is very important, the Nanoprocessor can handle interrupts in a max of 715ns, compare that to 12usec for the 6800.   The clock rate of the Nanoprocessor is 4 times faster but the efficiency of its interrupts and instructions are what really provides the difference here.

The clock rate difference (1MHz vs 4) really shows here, but the Nanoprocessor is also executed 3 times the instructions to do the same task, and still is faster.

Even using an external ALU compared to the Motorola’s internal ALU, the nanoprocessor is better then twice as fast (thanks here to its much higher clock frequency)

Full Handshake Data Transfer. Interfacing to the outside world was the main driver of the Nanoprocessor. Here we see that it can ‘talk’ to other devices much faster then the 6800

All instructions on the Nanoprocessor take 500ns to execute compared to the 1-10u for the 6800.

Today we do benchmarks based on framerates in games, or render times, but you can see that benchmarks were even important back then.  How fast a processor could handle things determined how fast the printer could be, or how fast it could handle external data coming in.  It’s no wonder that the Nanoprocessor continued to be made into the late 1980’s and many of them are still in use today running various HP equipment.

Nanoprocessor User Manual – October 1974

A big thank you to Larry Bower, the project lead and designer of the Nanoprocessor, who donated several prototypes, a complete mask set, and very early documentation on the Nanoprocessor (amongst some other goodies)

Documentation so ealy it has many hand written parts, and some corrections.  This had to be a very annoying oops if it wasn’t caught early on.  Even Engineers get their left and right mixed up on occasion


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News: New Server for CPU Shack Wed, 08 Jul 2020 17:50:19 +0000 It took way longer then it should have but over the last 5 weeks was transitioned to a new server.  We were hosted on a Media Temple GRID server, which got less and less suited for WordPress over the years so ended up with hundred of dollars in overages everytime i posted an article.  CPU Shack is now on a virtual dedicated server which should be faster and more flexible.  Next step will be to add SSL support, to keep up with current web guidelines.

If you notice anything not working, be sure to let me know.

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AMD Am29C327: How to Take a Picture of a Black Hole Sun, 14 Jun 2020 23:31:21 +0000

AMD AM29C327 Engineering Sample -1990

Recently I came across one of the more unusual members of the AMD Am29300 series.  These were a set of processor elements (multipliers, FPUs, ALUS, registers) AMD designed to support AM29000 CPUs as well as for the bases for custom CPU designs.  Some. like the AM29C323 multiplier found common use in video game and other applications.  Others like the AM29C325 32-bit FPU were used in educational experiments and research.  The 29300 (Bipolar) and 29C300 (CMOS) series are not particularly well known due to their obscure and often deeply specialized used.  At the top of the series lies the AMD AM29C327 Double precision (64-bit) FPU.  This FPU has a few tricks up its sleeves and is about as obscure in use as it gets….

The Am29C327 was on of the first chips made on AMDs CS-11A 1.2u processor (an enhancement of the 1.6u CS-11) .  It was first announced in 1987 with sampling to begin in late 1988.  The ‘327 contained over 250,000 transistors and was packed in a 169PGA package.  It is a IEEE754 compliant double precision FPU but also supports IBM and DEC formats.  It has 3 32-bit buses (2 for input and one for output) that, when multiplexed, allow for 64-bit maths.  Its little brother, the ‘325, only supports 32-bit math, and comes in a 145PGA package with around 30,000 transistors (11,000 gates).  So why does going to double precision involve nearly 10 times the transistor count?  It turns out that the ‘327 is more closely related to an actual CPU then a normal FPU.  The ‘325 has all of 8 instructions (add/sub, mult const subtraction and some conversions), while the ‘327 supports 58 instructions.  Of those 58 instructions 35 are Floating point, 1 is system management, and the other 22? Those are a full set of integer instructions.  The ‘327 actually supports more then just floating point.  Its internal ALU is a 64-bit 3 input design, allowing inputs from either the 2 external inputs, the output, a set of 8 64-bit registers, or a set of 6 constants.  Its instructions are 14 bits and it supports pipelining for even faster calculations.  Interestingly, pipelining can be disabled and the FPU will work in straight flow through mode.  So where is such a complicated chip used? Doing complicated math of course.

VLBA 25 Meter Antenna – NRAO

One such need for complicated math is in VLBI (Very-long-baseline interferometry).  VLBI is using a series of radio telescopes or antennas, spaced apart physically, to generate higher resolution data then a single antenna could.  The VLBA (Very-long-baseline array) is the largest of these, consisting of 10 25 meter radio telescopes spread across the USA.  The maximum distance between them is over 5500 miles, so with the right software and hardware, working together, they can emulate a single dish of several thousand miles diameter.  Production of this VLBA began in the late 1980’s and it went online in 1993.  One of the hardest parts of running a VLBA is correlating the data, data from each telescope must be precisely combined to generate the resulting observable output.  This is the job of the VLBA correlator, and as originally designed (and ran in such configuration at least into the 2000’s) this was based on a Motorola 68000 CPU driving multiple math cards.  These math cards (mainly responsible for FFT – Fast Fourier Transforms) were

M87 Black Hole – Imaged by Event Horizon Radio Array in 2017

managed by a single Dallas DS87C520 MCS-51 MCU that set up the data for a pair of AMD AM29C327 FPUs and a Xilinx FPGA to process.  A bit amazing that an 8-bit MCU was responsible for managing not one but two 64-bit FPUs, but in actuality all it had to do was route data to the proper places at the proper times, a gate keeper for the card.

Recently the VLBA, working together with other arrays to form the ‘Event Horizon,’ was able to take the very first ‘picture’ (radio data visualized) of an actual black hole.  Today’s arrays typically use modern CPUs, or even super computers (the LOFAR uses an IBM Blue Gene/P) to perform their correlation, this results in data output much quicker then the sometimes days it took the original VLBA to process data.  It all began with a 64-bit FPU from AMD in the 1980’s and scientists wanting to see what they could do.


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Chapter 2: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997 Wed, 13 May 2020 21:04:10 +0000 At the end of 2018, I started one project, which was called “Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997”. It was dedicated to the ALR Revolution 6×6 super server with six Intel Pentium Pro processors and a cost comparable to that of a brand new Ferrari in 1997. It took some 450 days and finally follows the continuation of the story, the super server received the long-awaited upgrade – six Intel Pentium II Overdrive 333 MHz Processors! For those years, such power was simply colossal, but how it compares with today’s and how much increased performance you will learn from this article.

I’ll admit 450 days is quite a long time, so I will briefly recall the contents of the previous series of the article.
And it all started like this: plunging into the world of mainframes and supercomputers , I wanted to try some super powerful system and the choice fell on the ALR Revolution 6×6 super server, which had six Socket 8 and supported up to 4 GB of RAM. For the late 90s, these were scary numbers, as well as its cost. One processor for such a system was estimated by Intel at $ 2675, and six were required, for one module of 256 MB of server memory it was necessary to pay $ 3500, and sixteen sticks were needed to get the coveted 4 GB of RAM.

A disk subsystem was also available with seven raid controllers and an 860 GB disk array, a twenty-kilogram power supply unit and the server itself … As a result, it was possible to reach amounts from 270 to 500 thousand dollars, and if you add here the inflation level over the years, these numbers will range from 435 to almost 800 thousand dollars. Now, in terms of performance, any low-cost computer will be faster than this monster, but the very fact of having such an opportunity in 2020, to feel the full power of that time, makes these large numbers insignificant, it is much more important to find and assemble such a monster.

ALR 6×6 Available Options

In the previous story, I studied performance with six Intel Pentium Pro processors with a frequency of 200 MHz and a 256 KB second-level cache and even overclocked all six copies to 240 MHz. As well as six top-end Intel Pentium Pro “black color” with a frequency of 200 MHz and a 1M L2 cache, which were able to overclock to 233 MHz. In my configuration, I had 2 GB of RAM standard FPM, 16 memory modules of 128 MB, which took over 4 minutes to initialize during the initial POST procedure.

Four gigabytes of RAM would bring this figure to 9 minutes, which is comparable to accelerating a train or taking off an airplane, although the latter can do it much faster. But then, having loaded at my disposal, six physical cores arrived at once, but without the support of MMX and especially SSE instructions.

Intel Pentium II Overdrive 333 MHz processor

The basis of any computer is the central processor. Intel Pentium Pro processors first appeared in 1995. Then there were the usual Pentiums without the Pro prefix, but this prefix in the name of the models said that these processors are positioned primarily as solutions for servers and workstations with their special Socket 8. The usual Intel Pentiums were installed in Socket 5 and 7. A significant difference between the Pro and the regular version of the Pentium desktop was the presence of a second-level cache in the Pro version, which, being on the same package, worked at the processor’s core frequency, thus allowing it to significantly increase performance.

For the various Intel Pentium Pro models, the L2 cache size ranged from 256 KB to 1 MB. Pentium Pro’s first level cache was 16 KB, of which 8 KB was for data and the same for instructions. For the subsequent Intel Pentium-IIs, the second-level cache worked at half the processor core frequency and amounted to 512 KB for all models, and it was located in the form of separate microcircuits on the cartridge at a distance from the CPU die itself. The L1 cache size was doubled in size to 32K, which offset the performance hit of the slower L2 cache.

Pentium Pro Slot 1 Slockets – Also made were Slot 2 versions.

The tested processors were produced at a 350 nm process technology. The number of transistors in the Pentium Pro totaled 5.5 million for the processor core itself and as many as 15.5 – 31 million were in the L2 cache memory, depending on its size. The L2 cache itself was located on a separate die near the CPU core. The processor had a free multiplier and the system bus frequency, depending on the model, was 60 or 66 MHz. Overclocking of the processor rested on overclocking the L2 cache, it the limiting factor.

CPU core on the right, L2 cache on the left

The Intel Pentium II Overdrive 333 MHz was a very interesting processor. This processor appeared, it can be said, thanks to the US Government, which funded a program to create supercomputers for modeling nuclear explosions and tracking the state of the country’s nuclear arsenal. The US government allocated funds for the construction of such a supercomputer, Intel won the tender and in 1997 handed over a turnkey supercomputer called “ASCI Red”.

ASCI Red consisted of 9298 200MHz Pentium Pro processors , all modules of the supercomputer were located in 85 rack cabinets. The total amount of RAM was 594 gigabytes, the disk subsystem consisted of 640 hard drives with a total disk space of 2 terabytes (consider now that this amount of storage is now provided by a single inexpensive hard drive). ASCI Red was the first supercomputer to break the line of 1000 GFLOPS or 1 teraflops. For several years in a row, it led the list of the TOP-500 fastest supercomputers in the world.

In 1999, modeling tasks became more complicated and the capacities of ASCI Red were already beginning to be lacking; an upgrade was needed. Programmers will always find a way to need more performance, no matter what you give them, especially if its for modeling the reliability of a strategic deterrent, or the weather, or…..  Intel won the tender again, and thanks to this event, a unique processor with a Socket 8 socket and the power of the Pentium II – Intel Pentium II OverDrive with a frequency of 333 MHz was born. The upgraded second-generation ASCI Red with 9632 processors after the upgrade provided 2.38 TFLOPS performance in the Linpack benchmark. Such high-quality characteristics allowed ASCI Red to hold the title of the fastest supercomputer until June 2000.

The Intel Pentium II OverDrive, which was the final stage in the evolution of Socket 8, belonged to the sixth generation of Intel processors (P6). The processor was announced in August 1998, despite its specificity, the recommended cost of the processor in batches of 1000 pieces was $ 599. Physically, this processor was installed in Socket 8, however, in fact, we see “Deschutes” core Pentium II , supplemented by a 512-kilobyte L2 cache operating at the processor core frequency, unlike the normal Deschutes core PIIs.  These are the only Pentium II processors (excluding the Celerons of course which had a on die cache and the Mobile Dixon core which had 256k of fullspeed cache) with a full speed L2 Cache. The Pentium II OverDrive VRM was integrated into the Pentium II OD module and lowered the supplied voltage from the motherboard (3.1-3.3V) to the required 2 volts for the PII core.

Pentium II Overdrive Module with Heatsink removed. CPU die is on the left and 512K of Cache on the right

The processor multiplier is locked at 5x, which with a 66.6 MHz FSB gives a total of 333 MHz. There are two versions of this processor, the first with SPEC – SL2KE, which is equipped with an active cooling system and SL3EA with a passive one. But the biggest plus is not only the increased processor clock speed, but also the support of the MMX instruction set and some others.

Since the motherboard supports multiplier changes up to x5.5, which would result in 366 MHz, I at the same time studied the properties of engineering samples of the Intel Pentium II Overdrive 333 MHz with SPEC Q0125. As the owner of such a processor told me, even the multiplier for this Engineering Sample is locked. Maybe it’s for the better, since acquiring six of these ES processors will be comparable to buying any top-end modern CPU, but first you need to find them somewhere else in such quantity.


It would seem that I spent more than a year to find and purchase six Intel Pentium II Overdrive 333 MHz processors, which now sell for an average of $ 200 at the world-famous flea market (, and got the maximum ALR Revolution 6×6 config, but as always there is no limit to perfection. But more about that below.

Mendocino is the name of the core of Celeron processors manufactured since 1998 in the performance of SEPP (Slot1) and PPGA (Socket 370). In 1999, Intel abandoned the Slot 1 form factor in favor of the familiar PPGA. Plastic Celeron processors were cheaper to manufacture, manufactured using 250 nm technology and had a built-in 128 KB L2 cache running at full processor core speed. The frequency range ranged from 300 to 533 MHz.

PPGA Celeron Processor – Full speed 128K of cache

And where does the Celeron Mendocino fit? The fact is that it is possible to launch Celeron processors in SMP (Symmetric Multiple Processor) and enthusiasts have been doing this for quite some time. Celeron at its core has the core of a full-fledged Pentium II, which, as you know, supports SMP. The difference between these processors is only in the L2 cache, Celeron L2 = 128 Kb, but the frequency can reach higher values of 533 MHz versus 450 for Pentium II.

Support for SMP is the presence of the BR # 1 signal, which is physically present in the processor itself, but has not been routed on the motherboard. Once this secret was discovered, the solution to the SMP problem was not long in coming. Enthusiasts picked up a soldering iron, and motherboards manufacturers ABIT and QDI, which were inspired by this idea, even released their serial products. Suffice it to recall the ABIT BP6 motherboard based on the Intel 440BX chipset with two Socket 370. (Editor’s Note: Oh the Days of running my BP6 with dual Celeron 366s happily running at 550MHz, Intel was not amused, but I was)

Further, there is one adapter from the company Powerleap model PL-ProII, which just allows you to install Intel Socket 370 Celeron processors  in Socket 8 motherboards, they are that closely related.

Therefore, it is theoretically possible to install six Intel 533MHz Celerons, which in total will give us 3200 MHz. Of course, I don’t know if all six processors will work, but the chance is not bad =) How much I did not surf the Internet, but I did not find the implementation of such bizarre ideas. I can find six Celerons without difficulty, but six Powerleap PL-ProIIs are unlikely. I had one such adapter, but I had to sell it in order to implement this project, as well as part of my other exhibits (( Therefore, if someone has one, or they know where to find it for responsible money, write to me in the discussion of this article or to my e-mail: (perhaps they could be recreated?)

We continue to fantasize LOL. In turn, if you expand even further the boundaries of imagination, and install another adapter with support for Pentium III processors with the Tualatin core in the Powerleap adapter, then who knows what can happen at all in the output, maybe such a sandwich….

The idea turned out to be interesting, so I do not give up hope that the next part or continuation of this story will someday be published. Perhaps in 2025.

Windows Vista Server

Having now at our disposal six Intel Pentium II Overdrive 333 MHz, which have already acquired support for MMX instructions and have risen one more stage of evolution along the processor ladder, I wanted to try to install an even more modern operating system.

Let me remind you, the last time I was able to install an operating system that was different from the recommended ones: Microsoft Windows NT Server 4.0 Enterprise, Microsoft Windows 2000 Advanced / Datacenter Server, which fully prevent you from running programs and tests written for the beloved Windows XP. As a result of lengthy experiments, we got such an OS: “Windows .Net Enterprise Server. Build 2600 Service Pack 2 ”, which is a semblance of a server operating system with a Windows XP kernel.

This time I wanted to raise the bar even higher and aimed at the family of operating systems based on the Windows Vista kernel. The ideal option was Windows Server 2008 Enterprise Edition (x86), but at first I decided to try installing Windows Server 2003 Enterprise Edition. Although it was written on paper about a hardware error in the core of the CPU of the Intel Pentium Pro family of processors and earlier Pentium II’s and the related problem of memory “leak” and the inability to work in the SMP mode of the above processors, I decided to check this in practice.

The result of this experiment is predictable – six Intel Pentium II Overdrive 333 MHz will not work as part of the ALR Revolution 6×6 running the Windows Server 2003 family of operating systems. Only one CPU is visible. And it’s a pity, this is how one hardware error puts an end to the happy future of such interesting processors.

The next step was to install Windows Server 2008 Enterprise Edition. For many parameters of the minimum configuration, ALR Revolution 6×6 met those requirements needed for the successful installation of this operating system. The installation process began safely, files began to be copied from the DVD-ROM’a to the SSD.

But after reboot I saw a window like this:

Again ACPI rears its ugly head … Saying that my config almost met all the minimum requirements, I did not mention that starting from Windows Vista all the kernels of this and subsequent operating systems are ACPI compatible, in other words, nothing will work without hardware ACPI. And the answer here lies in the BIOS of the  ALR Revolution 6×6, which was released long before the advent of ACPI.

But still there is a chance of installation, but this requires intervention in the BIOS code, but unfortunately I still can’t get a BIOS programmer. Back in the days of Socket 7, when the first revision of ACPI began to appear, motherboard manufacturers released new versions of their BIOS with support for this technology. I went through this as an example of an Asus P5A motherboard on the Ali ALADDiN V chipset for Socket 7 processors, when the ACPI BIOS Revision 1006 was released. This made it possible to install Microsoft Windows 7 x86 on this motherboard with an AMD K6-2+ processor.

An alternative solution to this problem was to look for early builds of Windows Vista Server. The initial project of this development was called “Longhorn”.

The image of this OS was found on the Internet (of course), burned to DVD and the installation process begin:

Everything went as usual, the files were copied, but upon completion of the copying process and reboot, the same error with ACPI was waiting for me.

Again, having spent a fair amount of time, I decided that I would start searching for the kernel of an operating system without ACPI support in earlier versions of Windows Vista or the Longhorn project. Perhaps they exist. If any early build is installed, then it will be easier with the implementation of SMP support. I tried different builds: 4042, 5098, as well as beta’s of the 2nd version. It should have turned out like this:

But the success of this event still ended with ACPI support from my test system. All tested builds still required ACPI support. As a result, I put this idea into a long drawer and decided to conduct all the tests on a proven Windows XP-like OS, where six Intel Pentium Pros felt great. To solve this problem, one head is not enough, so valuable ideas can be written in the discussion of this article, do not be shy 😉

Test system and test results

The test bench will include processors:
• 6x Pentium II Overdrive 333MHz L2=512 Kb
• 6x Pentium Pro 200MHz L2=1024 Kb
• 6x Pentium Pro 200MHz L2=256 Kb

• Unisys Aquanta HS6 (10140) chipset «Intel 450GX» (6x Socket 8);

Video card:
• PNY GeForce2 MX400 PCI 64Mb (Forceware 93.21);

• Kingston SSDNow V300 (60 Gb).

Performance testing was carried out in the “Windows Whistler .Net Advanced Enterprise Server, Build 2600, Service Pack 2, 3 in 1” author’s edition using the following software:
• Super Pi mod. 1.5XS (1M task)
• PiFast v.4.1
• wPrime v.1.43
• HWBOT Prime v.0.8.3
• CPU-Z v.1.87.0
• WinRAR x86 v. 5.40
• 7-Zip v.16.04
• AIDA64 5.50.3600
• SiSoftware Sandra 2004 SP2
• Cinebench 2003
• Cinebench R10


To start, a couple of single-threaded tests: Super Pi (1M task) and PiFast.

Super Pi mod. 1.5XS (1M task)
Minutes (less is better)

If we compare the performance of the fastest Pentium Pro with a clock frequency of 200 MHz and a 1M L2 cache then replacing one Pentium II Overdrive 333 MHz gives an additional one third of the performance. And if the number of such processors is the same as in ASCI Red – 9632 pcs., Then it turns out almost 3 million percent, if I calculated everything correctly.  You can see that the L2 cache size helps some but mostly this is a pure clock speed/architecture test.

PiFast v.4.1
Seconds (less is better)

In this test, the previous performance growth dynamics between the Pentium Pro and Pentium II Overdrive are preserved. Although this test loves the processor clock speed more than the cache size, even so, the overdrive gap from the 400 MHz Celeron turned out to be not very large. I really want to install six such Celerons in this system.

wPrime v.1.43

The first test that supports multithreading. For this article, I decided to measure the performance of not only six Intel Pentium II Overdrive’s, but also see what five and four processors are capable of, since the system allows even odd configurations to be used and scales well.

Seconds (less is better)

The performance criterion turned out to be six to four, the performance of six Pentium Pros corresponds to four Pentium II Overdrive, more precisely, overclocking Pentium Pro up to 233 MHz. Six “overdrives” have come off enough to match the performance of four server Xeon clocked at 400 MHz, or their performance is equal to one AMD Athlon XP with a PR rating of 2100+ and a frequency of 1733 MHz, released in early 2002. It took a little less than four years  for an ‘ordinary’ processor to match the performance of the 6x Overdrives.

Also of note adding a CPU (from 5 to 6 Overdrives) results in a very linear performance increase.  The ALR has very little overhead in handling the addition of processors.

HWBOT Prime v.0.8.3
Total score (more is better)

If in the past, the performance of a pair of gigahertz Intel Pentium III Xeon was something fantastic, now, 6 overdrive even managed to outperform this pair A slightly overclocked (by 5%) representative of a 64-bit new school – AMD Athlon 64 3800+ on Socket 939 is only slightly faster  despite the technological abyss between them.  Adding processors here resulted in less gains then in wPrime.

WinRAR x86 v. 5.40;
Kb/s (more is better)

The memory subsystem from the upgrade has not changed, all of the 66 MHz Fast Page Mode memory is used, but the numbers nevertheless increased due to brute processor power.

7-Zip v.16.04 (dictionary size 32 Mb);
Total score in MIPS (more is better)

Here again we see the effect of 6 to 4 or parity in the performance of 4 “overdrive” to six Pentium Pros. The slower memory subsystem interferes with archiving with more modern opponents, if it could be overclocked to 75 MHz …perhaps in the future.

AIDA64 5.50.3600
I present to you the results in this test package of six Intel Pentium II Overdrive 333 MHz.

And my favorite test is Cache and Memory Benchmark. See how the speed of the caches of both processors has increased. From left to right: Pentium II Overdrive 333 MHz and Pentium Pro 200 MHz (L2 = 1024 Kb).  Interestingly the L2 Cache write speed is nearly 25% faster on the original Pentium Pro, similarly its latency is better as well.

AIDA64 5.50.3600
CPU Queen, score (more is better)

The 6x Overdrives beat a 2.8GHz Pentium 4.  The P6 architecture was faster then the Netburst resulting in clock for clock performance gains.

AIDA64 5.50.3600
FPU Julia, score (more is better)

AIDA64 5.50.3600
FPU VP8, score (more is better)

Both of these FPU tests are less dependent on multiple cores, significantly impacting the ALRs score.  The Pentium III FPU also was greatly enhanced (with the addition of SSE amongst other things) which is readily apparent here as both the VP8 and Julia tests are heavily optimized for these

SiSoftware Sandra 2004 SP2
Arithmetic benchmark, MIPS (more is better)

SiSoftware Sandra 2004 SP2
Multi-media benchmark, it/s (more is better)

At least in the Integer test the 6x Pentium II Overdrives do well, the Multimedia test, being more FPU heavy, favors the PIII core, but at least we can say we beat an a quad Itanium?

Now we get to the most popular multi-threading number of crushing tests – Cinebench!
Cinebench 2003
points (more is better)

To the question, how many cores and which are better for rendering. There is a Pentium III-S 1400 MHz behind the Tualatin-S core, Socket 370, which is nearly as fast as the ALR The dual Sot 1 Intel Pentium III EB 933 MHz are quite a bit faster.  Clock speed (total available clock speed) as well as architecture matter a lot here.  Though you can easily see the weakness of the P4 core.

Cinebench R10
points (more is better)


Interesting numbers, isn’t it? You can try to find this test and look at your result. The final rendering of the previous system with six one-megabyte Pentium Pro with a frequency of 200 MHz was completed in 21 minutes and 14 seconds. Overclocked six cores to 233 MHz reduced this time to 18 minutes and 13 seconds, and for six Pentium II OverDrive it took 13 minutes and 32 seconds. The advantage is 4 minutes 41 seconds, and if we multiply this time by the entire number of processors in the ASCI Red supercomputer, we get 31 days full time 24/7 or 1/12 of a year of time savings, and this is already a tangible figure.

In the last article, I compared the six Pentium Pros in this test with the Intel Core i7-7800X, which rendered the final image in 20 seconds. This time it became interesting to me, and in how many seconds will the modern TOP from Intel – Core i9-10980XE be able to do this? I found a man, who owns this processor and he agreed to help me with the numbers and completed the tests. Now you can find out these final figures. So, with the default settings, the test was completed in 11 seconds, and when overclocking all 18 cores to 5 GHz in nine! And although the Cinebench R10 supports only 16 threads, you can still imagine the difference when you had to wait for a few hours on the desktop PC and literally a few seconds now to complete the same task.

And in the form of a small bonus, I will give the results of the integrated CPU-Z test:


It is time to make a conclusion. No doubt the ALR Revolution 6×6 and similar systems are fantastic. It’s even interesting to use such a machine at home. On one processor, you can hang the server of some network game C&C, StarCraft or Counter-Strike, for example, on the other the client of this game will be launched, on the third second, on the fourth will play mp3 in Winamp and there will still be a couple of free kernels that you can always something to load in the background. Two or four gigabytes of RAM should be more than enough for these and other tasks.

So far I have only one problem, what should take up 8 free PCI slots? Ha-ha )

For its time, such performance was unattainable for most organizations because of the ultimate cost of such systems. But the most interesting thing is that since the late 90s of the last century, progress has been rapidly gaining momentum and literally after 4-5 years, single-core processors for home use, costing hundreds of times cheaper, skipped this monster.

What we have now is not necessary to explain. The progress in the past 7 years has slowed significantly, however, since the “return” of AMD to the people with the brand name “Ryzen” and the corporate “Epyc” the process has revived significantly. And for this we cannot but rejoice. Perhaps in a couple of years the Cinebench R10 test will be executed on the nex gen (no no not THAT NexGen) processor in 1 second, then we can assume that the future has already come =)

I don’t want to put an end to this experiment, as long as there is room for striving, I will try to implement it, although it becomes more and more difficult every year, but I’ll come up with something…There is yet the possibility of faster RAM, overclocked Overdrives, or the elusive 6-way Celerons, or perhaps ACPI compliant BIOS.

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DEC M7260 KD11-A CPU: The PDP-11 Goes MSI Fri, 17 Apr 2020 05:52:02 +0000

PDP-11/05 Front Panel (pic from vintage_electron)

Back in 1972 DEC released the ‘budget’ PDP-11/05 16-bit computer.  The original PDP-11/20 had been released 3 years before and its CPU (the KA11) was based on simple TTL, its ALU could perform adds and that was all, which meant its designers had to get creative in implementing the instruction set.  By 1972 however things had changed, there still was no 16-bit processors available but there was now single chip 4-bit ALU’s.  The ALU was the famous 74181 and formed the heart of the KD11-A, DEC’s 4th processor design (the ‘third’ was the KB11-A which was similar but based on the faster 74S181 and used in the PDP-11/45 and released at the same time) .

The KD11-A consisted of a pair of boards, the M7260 Data Path Module and the M7261 Control Logic and Microprogram Module.  All the processor functional components are contained on these modules. The M7260 Data Path Module contains: data path logic, processor status word logic, auxiliary arithmetic logic unit control, instruction register and decoding logic, and serial communications line interface. The M7261 Control Logic and Microprogram Module contains: internal address detecting logic, stack control logic, Unibus control logic, priority arbitration logic, Unibus drivers and receivers, microbranch logic, microprogram counter, control store logic, power fail logic, line clock, and processor clock.   The M7260 was he brain, and the M7261 told it what to do, containing the microcode to implement the PDP-11 instruction set.  This was the first version (with the 11/45) of the PDP-11 that was microcoded.

Fairchild 934159 74181 MSI 4-bit ALU made on a Bipolar – This example from very early 1971

The KD11-A ran off a single 150ns clock resulting in a raw clock speed of 6.67MHz, however performance was limited by memory access speed. The PDP-11/05 supported up to 32K Words (64KB) of core memory and this memory could only run at a 980ns cycle time.  This limited the 11/05 performance to around 1MHz.  This was still quite good for 1972!.

The 74181 was capable of running at 42MHz (and 90MHz for the 74S181 Schottky TTL versions) but in a set of 4 this drops to about 27MHz (with the carry generator taking some time).   Speed, however, is usually limited by other things rather then the ALU itself.   The 74181 ALU contains the equivalent of 62 logic gates (170 transistors) and can perform 16 different arithmetic and logic functions on a pair of 4-bit inputs.  Ken Shirriff did an excellent die level analysis of a ‘181 thats worth reading.  It includes pretty pictures even.

DEC M7260 – Data Path for the KD11-B CPU – Dated July 1972

This particular KD11-A board is one of the very first made.  It is dated July 20th 1972, a month after the initial release of the 11/05.  The big white chip is a General Instruments AY-5-1012 UART.  To its right you can see thr 4 74181 ALUs.  Each is 4-bit and together they form a complete 16-bit ALU for the CPU. A 74150 Multiplexer helps determine what data goes where.  The 74182 is the Look ahead carry generator for the ‘181’s.  Most of the rest of the chips on the board are ROMs and supporting logic.  There is also 4 Intel C3101A 35ns SRAM chips, these are 16×4 SRAMs used as scratch pad memories and only were used in the very first version of the CPU (later versions replaced them with cheaper 7489 TTL versions).  The Scratch Pad Memory is what forms the registers for the CPU.  There are 16 16-bit registers with the the first 6, R0-R5 being general purpose registers and the rest special purpose such as the Program Counter, Interrupt Vector, etc.

M7261 Control module – Contains the microcode for the CPU (pic from

Another interesting point on this board is the very large amount of green wires running on the board.  These are called ECO wires, which are ‘Engineering Change Order’ wires, and are placed, by hand, after the board is made to correct faults in the board layout.  The goal is to not have these as they are expensive and delicate and can result in failures down the road, so further revisions of the board would have these fixed/implemented in the PCB.  You do not see these much at all any more as modern design/testing tools virtually eliminate the possibility of a faulty PCB layout making it into production.

When it was released the ~1MHz 11/05 cost $25,000, which in 2020 US Dollars is around $154,000.  THe PDP-11 series ended up being one of the most popular minicomputers, selling over 600,000 units over the years.  Later versions like the LSI-11 series moved the entire CPU to a single LSI chip, adding Extended Instructions, Floating Point Instructions, faster memories and other performance enhancements well into the 1980’s.   It was also widely comied, and enhanced in the Soviet Union and Russia.  It was on a Soviet PDP-11 clone that Tetris was developed, a game we are all rather familiar with.

Its amazing to see where computers have come in the span of but a few decades. but these important parts of history continue to be used.  Perhaps not the 11/05, but there are many PDP-11 systems still working away, typically inindustrial environments, ironically helping produce things likely far more advanced then themselves.

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The Intel N60066: Unwrapping a Mystery Fri, 20 Mar 2020 23:57:50 +0000

Fischer & Porter 53MC5 – The beginning of the Mystery

One day last summer, I was browsing the deep dark corners for processors, a fun, yet dangerous activity.  I happened upon a lot of PCBs from some older industrial automation equipment.  No real information was provided (those buying these boards clearly would already know what they needed).  They did however have a RTC, an EPROM a 16MHz crystal, and a large 84-pin PLCC.  That PLCC was marked as an Intel N60066.  Seeing such a large chip, surrounded by such components almost always means its some sort of processor or microcontroller.  The problem is, there is no known Intel 60066 part.  The chips were all made in the late 80’s and early 90’s and had  1980 and 1985 copyrights.  A 1980 copyright typically screams MCS-51, as that was when it was introduced and nearly all such chips bear an Intel 1980 mark.

Intel N60066

The boards themselves were dated from 1990 all the way to the early 2000’s (I bought a lot of them, another problem I have).  Some had the part number 53MC5 and the logo of Fischer & Porter.  Fischer & Porter has existed since the 1930’s and was a leader in instrumentation.  They were bought by Elsag Bailey Process Automation (EBPA) in 1994 which itself was swallowed up by ABB in 1999.  The boards design was largely unchanged through all of these transitions. Searching for documentation on the 53MC5 part number (its a Loop Controller) didn’t yield details on what the N60066 was unfortunately.  The only thing left to do was to set it on fire…

Unfortunately this is the only way I currently have for opening plastic IC’s (I need to get some DMSO to try apparently).  After some careful work with the torch and some rough cleaning of the resulting die it was readily apparent that this was an MCU of some sort.  The die itself was marked… 1989 60066.  This wasn’t a custom marked standard product, this was a custom product by Intel for this application, a very surprising thing indeed.  Unlike other companies such as Motorola, Intel was not well known for custom designs/ASICs.  This wasn’t their market or business plan.  Intel made products to suit the needs they saw, if that worked for the end user, great, if not, perhaps you could look elsewhere.  They would gladly modify specs/testing of EXISTING parts, such as wider voltage ranges, or different timings, but a complete custom product? Nope, go talk to an ASIC design house.  Its likely Fischer & Porter ordered enough of these to make it worth Intel’s effort.

Knowing this was an MCU and suspecting a MCS-51 further searching revealed the answer, and it came from the most unusual of places.  In 2009 the US NRC (Nuclear Regulatory Commission) determined there was no adequate Probabilistic Risk Assessment (PRA) for Digital systems in their agency, so set about determining how best to calculate risk of digitally controlled systems.  They analyzed a system used to control feedwater in nuclear reactors.  These are critical systems responsible for making sure the reactor is kept with the right amount of cooling water at the right time, failure of course is not an option.  The 53MC5 is what is used for controlling the valves.  In this document we find this nugget:

The controller is an 8051 processor on board an application-specific integrated circuit (ASIC) chip that performs a variety of functions.

Well that certainly helps, it is indeed a custom ASIC based on an 8051.  The report also provided a diagram showing the ASIC system.  This is an 8051 core with RAM/ROM (normal) as well as a Watchdog timer, a PAL, I/O Buffers, and Address Logic.

I sent a couple of these chips to my friend Antoine in France for a proper die shot, which he is quite amazing at.

Intel N60066 die – 8051 core on the left. Die shot by Antoine Bercovici

The 8051 core is on the left of the die, with its RAM/ROM.  A very large PLA occupies the bottom right side of the day.  In the upper right is presumably the external watchdog timer for the ASIC.  The lines crossing the die mostly vertically are a top metal layer used for connecting all the various sections.

The hunt for a new CPU/MCU is part of the thrill of collecting.  The satisfaction of finding out what a mystery chip is can be worth many hours of dead ends in researching it.  Its not common to have to go to the NRC to find the answer though.

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ESA Solar Orbiter: When SPARCs Fly Sun, 09 Feb 2020 23:58:20 +0000 ESA ERC-32SC

ERC-32SC – SPARC V7 MCM with RAM and MIL-STD-1553

In a few hours (assuming no more delays, UPDATE: Launch Successful) the joint NASA/ESA Solar Orbiter mission will launch on a ULA Atlas 5 Rocket out of Florida, USA.  This is a mission a long time coming for the ESA, which like NASA has to get its funding from the government, except in the case of ESA, that involves the governments of many countries in the EU, which can make planning a bit more tricky.  The mission was originally baselined in 2011 and hoped to launch in…2013…then 2017..then 2018 and finally a launch date in 2020.  The original proposal dates to the late 1990’s as a mission to replace the joint NASA/ESA SOHO Solar mission that had launched in 1995.  This creates some interesting design choices for a mission, as designing often happens before a mission is completely approved/funded.  For Solar Orbiter this is one of the main reasons for it being powered by a computer that by today’s standards is rather dated, space standards no less!

Solar Orbiter – ESA

The Solar Orbiter is powered by a processor designed by the ESA, the ERC-32SC.  This is the first generation of processors designed by the ESA.  It is a SPARC V7 compliant processor running at 25MHz and capable of 20MIPS.  The ERC-32SC is a single chip version of the original ERC-32 which was a MCM (Multi chip Module) containing 3 dies that made up the processor (the Atmel/Temic TSC691 Integer Unit TSC692 FPU and TSC693 Memory Controller) that was made on a 0.8u CMOS process.  The Single chip version was made possible by a processes shrink to 0.5u.  It was also made by Atmel,  (whom acquired Temic) and is commercially known as the TSC695 as it is designed for space use, is capable of handling a 300krad Total Ionizing Dose of radiation.  The computer used in the Solar Orbiter was built by RUAG and has two seperate ERC-32SC processor systems for redundancy.  Each of the ERC-32SCs are actually mounted on a MCM, the single chip SPARC, 48MB of DRAM (38 of which is used, the remainder is for Error Detection/Correction via Reed Solomon method), and a MIL-STD-1553 bus controller/RTC/IO are included in the package.

Fujitsu MB86900 – Original SPARC V7 Processor from 1987

The original specifications for this processor were developed back in the 1990’s, which is why it is a SPARC V7, equivalent to the very first Sun SPARC workstations of the late 1980’s powered by the likes of the Fujitsu MB86900/MB86901.  The ESA has developed several follow on processors since, all based on the later SPARC V8 architecture.  They are faster, and more efficient then the ERC-32SC, with some even being dual core processors.  They are known as the LEON-2 and the later LEON-3.  LEON2 has a 5-stage pipeline and no SMP support, while LEON3 increases the pipeline to 7-stages and adds SMP support.  LEON3 is also a VHDL core able to be added to many ASICS/FPGAs (LEON2 is a hard core).  The Solar Orbiter also has both LEON2 and LEON3 processors on board as well…

The Solar Orbiter caries with is 10 different scientific instruments, and each of them has their own processing subsystem, 9 of which are powered by LEON SPARC processors.  Its common for the main processor of a spacecraft to be the most powerful, but in this case the instruments each possess their own processor more powerful then that of the main spacecraft computer.   This is in large part due to many of these instruments being designed well after the original spacecraft bus and systems were baselined.  Payloads can be added/changed much later in the design of the spacecraft allowing their designers to use more modern computers.

Instrument Processor(s) Notes
Solar Orbiter OBC ERC-32SC – Atmel TSC695 Spacecraft Platform Processor
SoloHi LEON3FT – Microsemi RTAX2000 FPGA
LEON3FT – Cobham UT699
Two processors
SWA-HIS/EAS/PAS LEON2FT – Atmel AT697F up to 100MHz
STIX LEON3FT – Microsemi RTAX2000 FPGA
EUI LEON3FT – Cobham UT699 66MHz Single core
PHI LEON3FT – Cobham GR712RC Dual core up to 100MHz
SPICE 8051 + FPGA Long live the MCS-51

There is also likely more processors on this mission as well, but it can be hard to track them all down, nearly every system has its own processing (star trackers, radios/ attitude control etc)

So as you watch the launch tonight, and perhaps see science/pictures from the Solar Orbiter (or just benefit from its added help in predicting solar storms and allowing us here on Earth to prepare for them better) think of all the SPARCs it has taken to make it function.


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ARMing the Modems of the 1990’s Sat, 25 Jan 2020 01:11:59 +0000

Racks of external modems at an ISP back in the day

Back in the 1990’s I worked at several ISP’s in my hometown.  These were the days of dial up, and by working at the ISP I got free dial up access which my family and I enjoyed.  We had several racks (white wire racks) of external modems for dial in.  This was the most common solution for smaller ISPs.  External modems were usually more reliable, cheap and easy to replace if/when they failed (and they did).  They got warm so it wasn’t uncommon to see a fan running to help move more air.  Surprisingly I could only find a few pictures of a such installations but you get that idea.

By the late 1990’s as dial in access and ISPs grew to be major concerns dial up solutions became much more sophisticated.  Gone were wire racks of modems and in were rackmount all in one dial in solutions.  These included boards that hosted dozens of modems on one PCB. with their own processing and management built in.  One of the largest companies for these solutions was Ascend Communications.  Their ‘MAX TNT’ modem solution once boasted over 2 million dial up ports during the 1990’s.  Such was Ascends popularity that they merged with Lucent in 1999, a deal that was the biggest ever at its time, valued at over $24 Billion ($37 Billion in 2020 USD). It wasn’t just traditional ISPs that needed dial up access, ATM’s and Credit Card processing became huge users as well.  It wasn’t uncommon to try to run a credit card at a store in the 1990’s and have to wait, because the machine got a busy signal.  The pictured Ascend board has 48 modems on a single PCB, and would be in a rack or case with several more boards, supporting 100s of simultaneous connections.

Ascen CSM/3 – 16x Conexant RL56CSMV/3 Chips provide 48 modems on one board.

Ascend’s technology was based primarily on modem chips provided by Conexant (Rockwell Semiconductor before 1999).  Rockwell had a long history of making modem controllers, dating back to the 1970’s.  Most of their modem controllers up through the 80’s and early 90’s were based on a derivative of the 6502  processor.  This 8-bit CPU was more the adequate for personal use modems up to 33.6kbaud or so, but began to become inadequate for some of the higher end modems of the 1990’s.  These ran at 56k, supported various voice. fax, and data modes and handled a lot of their own DSP needs as well.  Rockwell’s solution was to move to an ARM based solution, and integrate everything on chip.

One of the results of this was the Anyport Multiservice Access Processor. It was called the Multiservice Access Process because it handled, voice, data, 33.6/56k, ISDN, cellular, FAX and several other types of data access, and it did so in triplicate.  The RL56CSMV/3 supported 3 different ports on one chip.  The CSM3 series was the very first ARM cored device Rockwell produced.  Rockwell had licensed the ARM810 (not very common), the ARM7TDMI and a ‘future ARM architecture’ (which was the ARM9) back in January of 1997.  In less then two

Conexant RL56CSM/3 R7177-24 ARM7 (non-V version has no voice support)

years Rockwell had designed and released the first AnyPort device, remarkable at the time.  The CSM/CSMV used the ARM7TDMI running at 40MHz and made on a 0.35u process.  The CSM/CSMV has another interesting feature, and thats the backside of the chip….

Take a look of the backside of the 35mm BGA chip, the ball arrangement is very unusual!  There is a ring of balls around the outer edge and 4 squares of 16 balls inside of that.  This is a multi-die BGA package.  There are 4 die inside one BGA package, three dies for the 3 Digital Data Pumps (DDPs) and a seperate die for the ARM7 MCU (which is made on a different process then the mixed signal DDPs).  Most of the balls in the 16×16 squares are to be connected to GND, and used for thermal dissipation (dissipating heat via the main PCBs ground plane).  Its not uncommon to see multidie packages today, but a multi die BGA package in 1999 was fairly innovative.

Surprisingly many of these chips are still in service, in today’s world of high speed broadband connections there are still many who are stuck on dial up.  As recently as 2015 AOL was still serving 2.1 million dial up customs in the US (out of around 10 million dial up customers total), which was still netting the company nearly half a billion dollars a year (by far their largest source of revenue at the time.  There is also still plenty of other infrastructure that still rely on dial up, ISDN, and even FAX services that require end point connections like the CSMV so its end is probably still a long ways off.

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Barn Find MOS MCS6502 – A Restoration Tue, 14 Jan 2020 23:18:42 +0000 ATARI Arcade BoardIn car collecting one of the ‘holy grail’ experiences is the ‘Barn Find’  finding and recovering a rare vehicle that has sat untouched, in some barn, or shed for some time.  They are often in rough, but original condition and can evoke much excitement.  As it turns out CPUs are not so different.  I recently purchased a very rough and very old ATARI Arcade board.

The pictures clearly showed it in terrible condition, with lots of oxidation and ‘stuff’ on it.  But it also had a white MOS 6502 processor.  These are some of the very first CPUs made by MOS and are rather desirable, as in addition to their use by ATARI, they were used in the very first Apple computer, the Apple 1.

When the board arrived it was clearly in bad shape, take a look at that nastiness.  What you can’t see, or rather smell, is the cow manure.  Clearly this board was in an actual barn at some point.  Probably relegated to such a retirement after serving in an Arcade parlor or bar for some time, either that or there was some bovin gaming going on.

You can see there is some oxidation on the lids of the various chips as well.  The ROMs and CPU are in sockets.  These sockets are nice, they are not a machine socket but rather a LIF, Low Insertion Force Socket, that helps as the pins on these chips are very delicate, and very possibly corroded.

Before attempting to remove the MCS6502 its best to see what I am working with, so I pulled some of the ROMs nearest to the 6502 to see how their pins looks and how easy they came out of their sockets.  They came out with not a lot of effort but you can see there is some oxidation on the pins.  What we do not want is the pins to be rusted TO the socket and then break off from the forces needed to remove the chip from the socket.

To help mitigate this risk I used some penetrating oil on the pins in the socket.  It seems strange to be squirting oil in the socket but it works.  It will help penetrate the rust and decrease the force needed to remove the 6502. After adding the oil I let the board sit on my heater in my office for several hours.  This helps the oil penetrate, as well as made my office smell like Deep Creep and cow manure, all in a days work.

Then I very gently work on removing the 6502, testing how tight it is and working it out from both ends.  It comes looses with very little drama, hopefully with all its pins intact….

Indeed!  All the pins are there.  The oil definitely helped as you can see 3-4 pins have some pretty good rust on them.  That is from moisture getting under the gold plating and bubbling up.  The pins at least seemed solid but now its time for some cleaning.

I have a wooden block I specifically made for these more delicate operations.  The chip can sit on the wood supporting the chip and the back of the pins, allowing them to be cleaning without being bent.

Various tools are used in this operation.

  • Cotton Swabs – for applying various cleaners and getting dirt off
  • Brake Cleaner – this is an Acetone based cleaner with Xylene, works very well for getting dirt off as well as removing the oils
  • Glass Cleaner – This is a very mild polishing compound, excellent for cleaning the pins of minor oxidation and cleaning the ceramic
  • Steel Wool – Use very very careful in long wiping motions, its easy to catch a pin wrong, but its needed to get some of the heavier rust off
  • Container – Hilariously this is the top of an old Lava Lamp, I use it to hold brake cleaner in for dipping the cotton swabs in
  • Magnifying glass – So I can see exactly how the rust looks, how deep, etc
  • Banana – For scale

This cleaning process takes me about an hour for this chip, it feel longer and can be nerve wracking, but slow and steady wins the race

After cleaning here is the MCS6502.  The pins still show a little oxidation but the worst is gone.  The ceramic is very clean and even the lid is nicer, with less red rust.  The lid is best to mostly leave alone, as the markings on these are very delicate, I was surprised they were intact at all. The biggest question though remains.  Does this MOS MCS6502 dated May of 1976 still work?  Its nearly 44 years old and who knows how long its been since 5 Volts has been applied to its NMOS transistors.

I stick it in the venerable 680x/650x Test Board, ensuring the board is configured right before applying power, and then…flip the switch…and the sight everyone wants to see Blinking LEDs!  It passes a function check with flying colors, and when further tested reveals that it is indeed old enough to have the (in)famous ROR bug.  The first MCS6502 did not support the ROR (Rotate Right) instruction.  It was in fact present, but behaved incorrectly.  Michael Steil over at has an excellent article on how the ROR instruction was broken.  MOS had chips with working ROR available in June of 1976.  That’s RIGHT after this particular 6502 was made, making it one of the very last ROR bug 6502s made.

Its fun to save and restore an old CPU, let alone one with so much history.  Not all such finds end up with such a happy ending.  Many old chips were set in black foam, that eventually rots the pins right off, always a pity, but today, we had success.

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Chips in Space: Making MILSTAR Thu, 02 Jan 2020 23:02:26 +0000

Milstar Satellite

Back in the late 1970’s having a survivable space based strategic communications network became a priority for the US Military.  Several ideas were proposed, with many lofty goals for capabilities that at the time were not technologically feasible.  By 1983 the program had been narrowed to a highly survivable network of 10 satellites that could provide LDR (Low Data Rate) strategic communications in a wartime environment.  The program became known as MILSTAR (Military, Strategic, Tactical and Relay) and in 1983 President Reagan declared it a National Priority, meaning it would enjoy a fair amount of freedom in funding, lots and lots of funding.  RCA Astro Electronics was the prime contractor for the Milstar program, but during the development process was sold to GE Aerospace, then Martin Marietta, which became Lockheed Martin before the 3rd satellite was launched.  The first satellite was suppose to be ready for launch in 1987, but changing requirements delayed that by 7 years.

Milstar Program 5400 series TTL dies

The first satellite was delivered in 1993 and launched in February of 1994.  A second was launched in 1995 and these became Milstar-1. A third launch failed, which would have carried a hybrid satellite that added a Medium Data Rate (MDR system).  Three Block II satellites were launched in 2001-2003 which included the MDR system, bringing the constellation up to 5.  This provided 24/7 coverage between the 65 degree N/S latitudes, leaving the poles uncovered.

TI 54ALS161A

The LDR payload was subcontracted to TRW (which became Northrup Grumman) and consisted of 192 channels capable of data rates of a blazing 75 – 2400 baud.  These were designed for sending tasking orders to various strategic Air Force assets, nothing high bandwidth, even so many such orders could take several minutes to send.  Each satellite also had two 60GHz cross links, used to communicate with the other Milstar sats in the constellation.  The LDR (and later MDR) payloads were frequency hopping spread spectrum radio system with jam resistant technology.  The later MDR system was able to detect and effectively null jamming attempts.

The LDR system was built out of 630 LSI circuits, most of which were contained in hybrid multi layer MCM packages.  These LSIs were a mix of custom designs by TRW and off the shelf TTL parts.  Most of the TTL parts were sourced from TI and were ALS family devices (Advanced Low Power Schottky), the fastest/lowest power available.  TI began supplying such TTL (as bare dies for integration into MCMs) in the mid-1980’s.  These dies had to be of the highest quality, and traceable to the exact slice of the

Traceability Markings

exact wafer they came from. They were supplied in trays, marked with the date, diffusion run (a serial number for the process and wafer that made them) and the slice of that wafer, then stamped with the name/ID of the TI quality control person who verified them.

These TTL circuits are relatively simple the ones pictures are:
54ALS574A Octal D Edge Triggered Flip flop (used as a buffer usually)
54ALS193 Synchronous 4-Bit Up/Down Binary Counters With Dual Clock
54ALS161A Asynchronous 4-Bit Binary Counters


Looking at the dies of these small TTL circuits is quite interesting.  The 54ALS161A marking on the die appears to be on top of the a ‘160A marking.  TI didn’t make a mistake here, its just that the the 160 and 161 are essentially the same device.  The 161 is a binary counter, while the 160 was configured as a decade counter.  This only required one mask layer change to make it either one.

ALS573 and ALS574 die

Similarly with the 54ALS574, which shares a die with the more basic ‘573 D type transparent Latch.  This was pretty common with TTL (if you look at a list of the different 7400 series TTL you will notice many are very similar with but a minor change between two chips).  It is of course the same with CPUs, with one die being able to be used for multiple core counts, PCI0E lanes, cache sizes etc.

Together with others they perform all the function of a high reliability communications systems, so failure was not an option.  TI supplied thousands upon thousands of dies for characterization and testing.  The satellites were designed for a 10 year lifetime (it was hoped by them

Milstar Hybrid MCM Command Decoder (picture courtesy of The Smithsonian)

something better would be ready, no doubt creating another nice contract, but alas, as many things are, a follow on didn’t come along until just recently (the AEHF satellites).  This left the Milstar constellation to perform a critical role well past its design life, which it did and continues to do.  Even the original Milstar 1 satellite, launched in 1994 with 54ALS series TTL from the 1980s is still working, 25 years later, a testament to TRW and RCA Astro’s design.  Perhaps the only thing that will limit them will be the available fuel for their on-orbit Attitude Control Systems.

While not necessarily a CPU in itself these little dies worked together to get the job down.  I never could find any of the actual design, but it wouldn’t surprise me if the satellites ran AMD 2901 based systems, common at the time or a custom design based on ‘181 series 4-bit ALUs.  finding bare dies is always interesting, to be able to see into whats inside a computer chip, but to find ones that were made for a very specific purpose is even more interesting.  The Milstar Program cost around $22 Billion over its life time, so one must wonder how much each of these dies cost TRW, or the US Taxpayer?

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