The CPU Shack Museum http://www.cpushack.com CPU History Museum for Intel CPUs, AMD Processor, Cyrix Microprocessors, Microcontrollers and more. Wed, 30 Sep 2020 04:47:45 +0000 en-US hourly 1 https://wordpress.org/?v=5.5.1 Aircraft Instrumentation, Bitchin’ Betty and an 80C86 CPU http://www.cpushack.com/2020/09/29/aircraft-instrumentation-bitchin-betty-and-an-80c86-cpu/ http://www.cpushack.com/2020/09/29/aircraft-instrumentation-bitchin-betty-and-an-80c86-cpu/#respond Wed, 30 Sep 2020 04:46:53 +0000 http://www.cpushack.com/?p=23286 Quite the combination I know, but of course all related.  Last week I got some boards in that were quite interesting.  They were all fairly early serial numbered, from the 1980s and military in design.  Now one thing about anything military is identifying it is pretty hard to do, especially when it hails from an […]

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F-15 with P4 Instrumentation Pod – Looks like a missile under the wing, with blue and red stripe.

Quite the combination I know, but of course all related.  Last week I got some boards in that were quite interesting.  They were all fairly early serial numbered, from the 1980s and military in design.  Now one thing about anything military is identifying it is pretty hard to do, especially when it hails from an era before the Internet.  Many records from the 1980s have made it online, but OCR and transcription errors abound, a single wrong digit can turn an item made for a A-4 Skyhawk into a new blade from a lawnmower or a shiny new Navy mess tray.

Thankfully these boards all had a CAGE code which the US uses to identify each and every supplier.  In this case that code was 94987 which is Cubic Defense.  Cubic didn’t make lawnmower blades or mess trays but they did make a lot of instrumentation systems for aircraft (and they continue to do so).

F-16 with blue training pod under its left wing)

It turns out that training fighter pilots is best done without having to use live weapons, for obvious reasons, but in all other aspects should remain as true to lifer as possible, and then be able to be analyzed after that fact in order to learn from mistakes, and see who gets bragging rights for pulling the most G’s.  This means that the aircraft has to send and receive data as it would in combat, threat warnings have to go off when targeted, missiles have to be ‘launched (while being captive) at the appropriate times, and every aspect of the flight must be recorded, speed, roll rates, altitude, etc.

Cubic made pods, that attached to one of a fighters weapon hardpoints (typically the outermost) that did exactly that.  These pods interface with the aircraft’s flight systems (using the standard 1553 bus) as well as with ground based systems on the training range, forming a complete picture of what is going on between all the aircraft taking part.  These particular boards are from Cubic’s second generation digital pods, the P4 series (the first gen was, the P3). Specifically the P4A series.  Each pod contained a vast amount of sensors, antennas and instrumentation to monitor and record what was happening, as well determine if a missile as ‘launched’ to or from the fighter.

Cubic 185200-1 with Harris ID80C86 – The brains of the AN/ASQ-T25 P4AM Training Pod

At their heart was a Harris or Intel 80C86 processor, (Harris actually did the CMOS conversion on the 8086).  This is one of the earliest applications of the CMOS 8086.  In this case the 80C86 is running off of the normal 8284A clock generator and a 13.5MHz crystal. This results in a processor frequency of 4.5MHz, a bit under its 5MHz rating.  This is pretty typical of military applications, it generates less heat, draws less power, and gives more margins.  This particular board has a industrial spec CPU, later production versions had a full military qualified part (this board was a prototype).

1553 Bus Controller Board made by Cubic

A separate board handled 1553 bus communications (for talking to the rest of the aircraft).  Likely many other support boards were also included, but one of the more interesting ones contains a National Semi MM54104 DIGITALKER chip.  The DIGITALKER is a integrated circuit digital speech synthesizer designed by National based on the work of Forrest S. Mozer, thus his name being on the chip

Cubic 188135-1 with very early National Semiconductor DIGITALKER – This is from a AN/ASQ-T20 P4AX Training Pod (A P4A without Altimeter support)

This is a very early DIGITALKER chip, note the patent number on it: 4124125, which is a misprint, it should be 4214125 (the other one is for a heat exchanger), which appears on later examples of the DIGITALKER.  Using compressed voice samples int he two MD2764 EPROMs on the board the DIGITALKER synthesizes a voice, which is often called ‘Bitchin’ Betty.’  This voice can warn the pilot of various things such as missile locks, targeting, or in some cases, what maneuvers to perform to not become nose art on your enemies plane.  The pod has its own as it is simulating warning that would come if there was in fact an actual missile launch.  The pod can receive telemetry from the ground, and other pods that a simulated missile launch has occurred, and provides the needed inputs to simulate what happens.

Cubic P4 Pod Memory – 1 Mbit in a Intel 7110-4 module. This is a very early prototype of the board, hand made and hand wired.

The pods also record the likelihood of the missile attack being successful or not, useful for scoring the mock dogfighting. This and other data was stored on 1 Mbit Intel 7110-4 Bubble memory modules,  These were the hot new thing in the late 1970’s, providing a fairly fast form of nonvolatile memory. Today FLASH memory does the same ting, in s much more easy to use format.

Backside of the mission memory board. All handwired. Debugging had to be fun.

 

All of this is powered by the lowly 80C86 processor.  These P4A pods were all retired in 2006-2010 and replaced by much more advanced P5 instrumentation pods.  The P5 has longer range (both air to air and air to ground) much better encryption support (always a bummer when your dogfight gets hacked) as well as live monitoring (no more having to download all the data after the fact). Perhaps someday I’ll find some boards from a P5…..give it 40 years or so.

 

 

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Finding the Limits of the Socket 8 http://www.cpushack.com/2020/09/09/finding-the-limits-of-the-socket-8/ http://www.cpushack.com/2020/09/09/finding-the-limits-of-the-socket-8/#comments Thu, 10 Sep 2020 02:38:13 +0000 http://www.cpushack.com/?p=23238 Socket 8 processors have something magical and I really enjoy working with them. Earlier I wrote about them more than once and it would seem that everything has already been said, but in this article you will find out which PC configuration is truly the fastest on Socket 8, although it never existed in reality. […]

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Socket 8 processors have something magical and I really enjoy working with them. Earlier I wrote about them more than once and it would seem that everything has already been said, but in this article you will find out which PC configuration is truly the fastest on Socket 8, although it never existed in reality. I just gave this platform what it never had, it’s like giving the first representatives of the Skylake processor architecture, which was released back in 2015, DDR5 and PCI-Express 4.0 today.

Before starting another fascinating story about Socket 8 and the processors that were installed there, I will give links to my previous experiments:

Chapter 2: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997
and what got us started…
Part 1: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997

As you can see, my close acquaintance with this socket has existed for a long time and over the past few years we have clearly managed to make friends. It would seem that all Socket 8 processors have been studied and tested in various configurations, including an insane configuration of six processors in such a monster as the ALR Revolution 6×6. But quite recently I got my hands on a motherboard made by ASUS, which gave me the opportunity to take a fresh look at the use of processors and the performance they are able to give in a newer platform.

What is this board and what chipset is it based on? To name the heroine of today’s article, I will first dwell on the main chipsets for Socket 8 processors. The first chipsets for Intel Pentium Pro processors appeared in November of 1995, 25 years ago. Already at that time, they understood that the future was behind the parallel execution of various tasks. The Intel 450KX chipset, codenamed “Mars”, was introduced for workstations, and the Intel 450GX “Orion” for servers. Mars allowed for dual-processor configurations, and the Orion officially supported up to four physical processors. Although on the example of the super-server ALR Revolution 6×6, which is based on Intel 450GX, the number of processors could have been much larger and could easily double the official figure.

Nowadays the term chipset is often associated with a single chip located on the motherboard, but when applied to the first chipsets for Intel Pentium Pro processors, we are dealing with the physical seven chips that made up the “number of special chips” or “chipset.” These chipsets supported slow FPM DRAM standard RAM, the server GX chipset could operate with 4 GB of such memory, while the KX “was content” with 1 GB support (Intel figuring a workstations needed less RAM then a server). By the standards of the second half of the 90s, these were immense volumes of RAM

In May 1996, a more progressive chipset appeared – Intel 440FX “Natoma”, which quickly began to replace older system logic sets. Intel 440FX itself already consisted of a pair of microcircuits, support for SMP, faster EDO / BEDO DRAM memory types along with the outdated FPM DRAM (though limited to 1GB max of RAM), a new version (2.1) of the PCI bus standard, as well as support for Intel Pentium-II processors were announced.

Most motherboards based on the Intel 440FX “Natoma” chipset have a physical design in the form of a Socket, where the processor was installed, but there were exceptions with a few using the new Slot 1 slot, where the first Pentium-II and Pentium Pro were installed through special slot adapters. A good example is the ASUS KN97-X motherboard with the included Socket 8->Slot 1 adapter called the ASUS C-P6S1.

ASUS KN97-X motherboard with ASUS C-P6S1 slocket adapter

Each manufacturer of such slot motherboards produced their own slot adapters, but due to their small circulation, finding them is now problematic. Socket 8 processors feel good in such adapters and the presence of a more modern infrastructure of such motherboards obviously contributes to an increase in performance. But Intel, having released the Intel 440FX chipset, decided to stop further support for its Socket 8 processors, although it could really have extended their life cycle.  Why just sell people a new motherboard chipset, when you cold ALSO force them to buy a new CPU to go in it?

Slocket 8 – Socket 8 to Slot 1 Adapters

Getting the Pentium Pro to work on the 440LX based Slot 1 ASUS KN97-X is not easy, you need a special BIOS version for the Pentium Pro, since the motherboards were designed mainly for Intel Pentium II processors. Therefore, each time you want to change the generation of processors, the user had to install a new BIOS chip, otherwise, beyond the POST screen, on a BIOS designed for Pentium II, you will not see anything.

Intel AL440LX motherboard by Intel

In 2016, I was able to first “make friends” with Pentium Pro and the next set of logic from Intel for Pentium-II processors – Intel 440LX “Balboa”, which was presented in August 1997. The Intel 440LX “Balboa” was already fundamentally different from all previous Intel chipsets. There was support for high-speed SDRAM memory, an integrated IDE controller with support for Ultra DMA-33, and, most importantly, there was support for a high-speed graphical interface – AGP, which worked in 2x mode.

Dual lLot 1s on a 440BX

Later, compatibility was mastered with the popular Intel 440BX “Seattle” chipset, which appeared in April 1998, which for a long time was used in computers by hundreds of millions of users. The main feature of this chipset is support for 100 MHz system bus and the ability to comfortably overclock Slot processors. The 440BX still supported the Ultra DMA-33 standard , but the speed of the disk system has increased at least twice as compared to the old PIO mode on the first chipsets for Pentium Pro. Motherboard manufacturers went further and in a number of advanced products it became possible to set the FSB frequency up to 155 MHz and in exceptional cases even up to 200 MHz (ABIT BE6-II).  The 440BX was also the first chipset where a heatsink on the chipset (North Bridge ) became common.

The FSB frequency of all Pentium Pros and the Pentium II Overdrive 333 MHz is 66 MHz. The L2 cache operates at the core frequency, in contrast to the Pentium II, where the external L2 cache operates at only half the speed of the CPU core. The L2 cache size of the Pentium Pro is also available in capacities up to 1M making it oh so delicious =). The very idea that a retro dream system with a processor the size of a cigarette pack can be run even faster makes me apply all possible efforts to implement it. The unlocked multiplier of Intel Pentium Pro processors allows using not only the standard configuration (system bus x processor multiplier) 66 MHz x3, but also 100 MHz x2, thus increasing the bandwidth of all PC components, and if you add a high-speed SSD to the Ultra DMA-33 controller , then the responsiveness of the retro system increases significantly!

The presence of an AGP video card and modern discrete controllers using PCI expansion cards generally make such a system unattainable in terms of performance in relation to the reference from the mid-90s.

It would seem then that it is impossible to get much faster than Intel 440BX. But no, there is an alternative from VIA Technologies and its chipset for SLOT 1 motherboards for Intel processors –  the VIA Apollo Pro133A. This chipset appeared much later (late 1999) than the Intel 440BX in the computer market, so it immediately gave a new user the following advantages over motherboards based on the 440BX chipset. The disk subsystem has doubled in performance due to the native support of the Ultra DMA-66 protocol, and the exchange rate with the graphics accelerator has also doubled due to the ability of the AGP interface to work in 4x mode. It is also worth noting that VIA-based motherboards support the correct AGP bus frequency divider when using the system bus of 133 MHz and higher.  It should be noted that the Pro133 and Pro133A were the first chipsets for Slot 1 to officially support 133FSB (there were some overclock BX133 boards previously but the BX never officially supported it)

In numerous comparisons and reviews of those years, these two chipsets, despite the fact that they appeared on the market more than a year apart, showed almost identical performance, but in some tests they left each other behind by up to 5%. There was more technological superiority behind the VIA chipset however. In addition to all of the above, the VIA Apollo Pro133A chipset supported up to 1.5 GB of RAM, versus only 1GB  for Intel 440BX, and this memory functioned asynchronously with respect to the system bus. Besides, the RAM frequency could be 33 MHz higher than the FSB frequency. In subsequent VIA chipsets for the Socket 462 platform for AMD Athlon processors, this solution with asynchronous bus operation continued to be used with good success.

In addition to these main differences, there was also support for hardware monitoring, and a doubled number of supported USB ports, as well as the presence of an AC’97 audio codec. What happens if you put all these technologies into an ASUS motherboard? The answer is ASUS P3V4X.

ASUS P3V4X – VIA Apollo Pro 133A

So, what is the ASUS P3V4X motherboard? The ASUS P3V4X motherboard supports Intel Pentium II / III processors, four RAM slots make it possible to use 2GB of PC133 SDRAM, as well as Virtual Channel Memory. The motherboard has a universal AGP 4x slot, thanks to which you can install the fastest video accelerator from Nvidia – GeForce 7 series. 6 PCI slots and 1 ISA slot make it possible to connect any external expansion cards, including a tandem of a pair of 3Dfx Voodoo2 operating in SLI mode.

ASUS decided to use the older 596B southbridge instead of 686A on its board, as a result of which the P3V4X lacks the AC’97 sound controller and AMR slot, but that’s for the best in this case, you can add your own sound from Creative to your taste, and with a lone ISA slot, why not stick in a AWE64 Gold.

P3V4X with C-P6S1 Slocket and Pentium Pro

From an overclocking point of view, this is also an excellent board that allows you to increase the FSB up to 166 MHz, either using dip-switches or directly from the BIOS. The ability to choose timings for RAM and increase the voltage on the processor are also available.

The choice of the asynchronous mode of operation of the RAM is clearly demonstrated in the photo of this option in the BIOS of the ASUS P3V4X motherboard.

FSB/Memory Rations

I wonder what happens when the 1995 Pentium Pro and the Pentium II Overdrive are installed in a 2000 vintage motherboard that supports Intel Pentium III Coppermine processors? You will receive all the answers to these two questions and more by reading this article to the end.

Test bench and test results

The test bench will include the following Processors:
• Pentium Pro 200 MHz – 1024 Kb L2
• Pentium II Overdrive 333 MHz – 512K L2
• Intel Pentium II 333 MHz Deschutes 512K L2 (half core speed)
• Intel Pentium IIIE 667 MHz Coppermine 133FSB – 256K L2
• Slocket 8 slocket adapter ASUS C-P6S1.

Motherboard:
• ASUS P3V4X, chipset VIA Apollo Pro133A – Slot 1
Memory:
• 256 МB SDRAM PC133 (CL2);
Graphics card:
• Gainward Bliss 7800GS 512 МB, AGP@4x (Forceware 169.21)
SSD:
• Kingston SSDNow V300 (60 Gb)

There is a bit of irony in using a video card with more RAM 512MB) then the system (256MB) its in.  Its also GDDR3 RAM running at 600MHz with a core clock of 425MHz.  Clearly the GPU will not be a bottleneck in this system (though it could be limited by the AGP 4X slot, as this card is a AGP 8X design)

Testing was conducted on Windows XP, Service Pack 3 using the following software:
• Super Pi mod. 1.5XS (task 1M)
• PiFast v.4.1
• wPrime v.1.43
• WinRAR x86 v. 5.40
• AIDA64 5.50.3600
• Cinebench 2003
• 3DMark 2000
• 3DMark 2001 SE
• PCMark 2004.

And now a little about what, how and with what will be compared. First, let’s see what results will be obtained on the ‘modern’ VIA Apollo Pro133A chipset with the processor/RAM mode in the 66/66, 66/100, 100/133 MHz ratio and further overclocking. That will give the asynchronous mechanism of operation of RAM in relation to the system bus for Intel Pentium Pro and Pentium II Overdrive processors.

Some Software Engineering was needed to make the board work…

Then the obtained results will be compared with reference platforms of that time, and also the classic Intel Pentium II operating at the same clock speed (but with its half speed L2 cache) aswell as  the Pentium II Overdrive will act as the competition. I also added an Intel Pentium IIIE 667 MHz with the “Coppermine” core, which has the same multiplier (x5) as the Intel Pentium II Overdrive, in order to compare both processors at the same clock speed and the same FSB frequency. It’s time to see what happened in the end and what the history of these processors could be if Intel gave the user a little more freedom.

Tests

Super Pi mod. 1.5XS (task 1M)
Minutes (less is better)

The first thing that can be stated is the difference in the operation of RAM with an increased clock frequency in relation to the system bus! This can be seen in the example of the Pentium Pro. The difference from the transition of “old” Intel 440GX chipsets to new ones is also clearly visible. In a test that calculates the value of pi with millions of decimal places and lasts 9 minutes and 3 seconds on the classic platform, on the VIA platform the same processor saves more than one minute of time, performing the same task in 8 minutes and 2 seconds, using the frequency FSB/DRAM formula – 66/100 MHz.

By moving or overclocking the FSB frequency of the processor to 100 MHz, the performance increases even more. It should be noted that the capacious 1 MB L2 cache functions perfectly at this frequency, and its stability limit is in the 110-112 MHz FSB limit.

A similar picture emerges with the Intel Pentium II Overdrive. From the transition from Intel 440GX to VIA we have a whole minute of time savings in calculations. At a frequency of 500 MHz the Intel Pentium II Overdrive the advantage of this processor is undeniable, only the Intel Pentium III with the “Coppermine” core is able to surpass the achieved result of the leader. But there is already a technological gap between these two processors, with a faster core design and instruction set.

PiFast v.4.1
Seconds (less is better)

In this test, the same dynamics of performance growth remains, although the test focuses more on the processor capabilities of the system and less on the RAM. Hence the interesting result of the Pentium Pro overclocked to 220 MHz, which outperforms the Pentium II 266 MHz on the i440LX chipset. Against the background of all this, the result of an ordinary Intel Pentium MMX 200 MHz on Socket 7 looks ridiculous, and the Socket 8 platform is just a real modern analogue of HEDT (High End DeskTop) from Intel.

wPrime v.1.43
Seconds (less is better)

wPrime once again shows that the situation is not changing and the performance gain of the VIA platform is quite significant. In this test, the Intel Pentium II Overdrive overclocked to 500 MHz managed to outperform the equal-frequency Intel Pentium III. The 512K L2 cache (twice that of the PIII)  played a role here.

WinRAR x86 v. 5.40
Kb/sec (more is better)

WinRAR, like any archiver, loves very much that the communication channel between the processor and RAM is as wide as possible, hence the higher the FSB frequency, the better the result. Of course, the frequency of the RAM and the processor itself plays an important role. Of all the obtained values, the result of the 333MHz Intel Pentium III stands out well, at which the system bus frequency was equal to a modest 66 megahertz, and the RAM worked at a frequency of 100 MHz. And under such conditions, the Pentium III bypassed even the Pentium Pro, operating at 220 MHz with a 110FSB and 146 MHz for RAM. We can state that Intel has designed the Pentium III core very well in comparison with previous generations of processors and the performance gain is quite impressive.

Also impressive is the Pentium Pro 200 running at 100/133 just beating a Pentium II Overdrive 333 at 66/66.  That shows very clearly the FSB/Mem clock bias of this test.

Against the background of all this, four Pentium II OverDrive 333 MHz in a system based on the i450GX chipset deliver speeds slightly higher than one Intel Pentium III with a frequency of 500 MHz.

AIDA64 5.50.3600
This is how Overclocked processors are identified by AIDA64 and CPU-Z

For greater confidence, I will also present the CPU-Z validation of the Pentium II OverDrive processor overclocked to 525MHz. At this frequency, the processor was not 100% completely stable, but it still has some margin of safety, this is primarily the merit of the motherboard – ASUS P3V4X.

AIDA64 5.50.3600
CPU Queen, score (more is better)

(click for Larger)

AIDA64 5.50.3600
FPU Julia, score (more is better)

(Click for larger)

But, probably, the most interesting thing is to look at the results of the Cache & Memory Benchmark, where at one frequency you can see how much the VIA Apollo Pro133A has gone ahead of the Intel 440FX, as well as a radical revision of the algorithm of the core and memory cache of Pentium II and Pentium III.

 

Cinebench 2003
score (more is better)

There is no difference in rendering on a single core with an equal processor frequency and various combinations of memory subsystem operation. The only remark is related to the Pentium II 333 MHz, which is inferior to other competitors with the same clock speed. And the blame for the defeat is the L2 cache, which operates at half the clock speed of its competitors. Pentium III, as always, won the victory among all test participants.

3DMark 2000, 3D score
score (more is better)

The lack of results for Intel Pentium Pro processors is explained by the absence of MMX instructions, without which this benchmark cannot work. But in the “3D parrot meter” of 2001 there is no such limitation, but even in spite of this it is clear that there is still a performance gain from switching to a faster operating memory.

At 333 MHz, the Pentium II lost out to the Pentium II Overdrive, as it should be (due to the ODs faster L2 Cache), but the Pentium III went into an uncatchable lead.

3DMark 2001 SE
score (more is better)

Here all the processors are already assembled, it’s a pity it is impossible to install a powerful AGP accelerator in a motherboard based on the Intel 440FX chipset, but in any case, such a combination would still be a loser.

PCMark 2004
score (more is better)

This is the last test within the framework of this article and it once again shows that a Socket 8 system in conjunction with the VIA Apollo Pro133A chipset is an uncompromising solution in terms of building a retro system and the possibility of its further expansion.

Conclusion

This experiment showed that the impossible is sometimes possible and often manufacturers of processors or motherboards artificially do not allow further operation of their components for a long period of time for economic reasons. Such artificial technical barriers are eliminated either by updating the BIOS of the motherboard, or by minor intervention in the circuitry, or by replacing the cooling system altogether, which we all recently observed in the example of the running on motherboards based on the very first chipset for processors with the Skylake microarchitecture – Z170 and processors that this chipset does not officially support. And such examples are not isolated, so such tests as we did here, perhaps will happen again with today’s processors 20 years from now.

It is good to do such experiments as long as the platform is available, but even after a couple of decades, one can understand why this happened “then”. In the configuration we tested, the Socket 8 system in conjunction with the VIA Apollo Pro133A chipset provides the highest performance ever obtained for Socket 8 processors and the ability to use the asynchronous mechanism of RAM operation where its frequency is higher than the system bus frequency is a positive decision.

It would seem that the end of this story has been set, but as always there is one (yes, one, there is always one) exception – the existence of a motherboard manufactured by ABIT, the SH6 with an i815E chipset and a Slot 1 interface. I have been looking for this board for many years and so far I have not been able to find it, but it would be very interesting to try to launch Socket 8 processors on it and compare the results obtained on the VIA platform.

Abit SH6 -Intel i815 Based Slot 1

Summing up today’s experiment, I want to note that I have not yet put an end to experiments with Socket 8, I’ll see you here.

Another article by max1024 – Edited by CPUShack

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HP NanoProcessor Mask Set http://www.cpushack.com/2020/08/20/hp-nanoprocessor-mask-set/ http://www.cpushack.com/2020/08/20/hp-nanoprocessor-mask-set/#comments Thu, 20 Aug 2020 22:10:29 +0000 http://www.cpushack.com/?p=23215 Since we have a complete, and very early mask set of the HP NanoProcessor (donated by Mr Bower, thank you) it seemed fitting to scan them in (tricky at 600 dpi and 6 scans each (they are around 40x60cm) then I sent them over (500MB) my friend Antoine Bercovici in France to stitch and clean, […]

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Since we have a complete, and very early mask set of the HP NanoProcessor (donated by Mr Bower, thank you) it seemed fitting to scan them in (tricky at 600 dpi and 6 scans each (they are around 40x60cm) then I sent them over (500MB) my friend Antoine Bercovici in France to stitch and clean, as well as remove the background.  THat allowed this cool animation of the mask being built.
These are made from a set of 100X Mylar masks

Here you can see how the 6 different mask layers are built up.  The last mask layer (black) is the bonding pads
Each individual layer is also shown, some are very simple, while others contain a lot more.

In the lower left corner of the masks you can see their layer number 1B 2A 3A…etc

You can see the original HP part number on the mask 9-4332A as well as ‘GLB’  GLB is a composition of the initials of the two designers of the chip: George Latham and Larry Bower.

Here is a larger version as well: HP NanoProcessor Mask Set

 

 

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The Forgotten Ones: HP Nanoprocessor http://www.cpushack.com/2020/08/09/the-forgotten-ones-hp-nanoprocessor/ http://www.cpushack.com/2020/08/09/the-forgotten-ones-hp-nanoprocessor/#comments Sun, 09 Aug 2020 22:18:31 +0000 http://www.cpushack.com/?p=23173 Back in the 1970’s the Loveland Instrument Division (LID) of HP in Colorado, USA was the forefront of much of HP’s computing innovation.  HP was a leader, and often THE leader in computerized instrumentation in the early 1970’s.  From things like calculators, to O-scopes to desktop computers like the 9825 and 9845 series.  HP made […]

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Original Nanoprocessor prototypes from 1974-75. Note hand written wafer number, open die cover and early part number (94332)

Back in the 1970’s the Loveland Instrument Division (LID) of HP in Colorado, USA was the forefront of much of HP’s computing innovation.  HP was a leader, and often THE leader in computerized instrumentation in the early 1970’s.  From things like calculators, to O-scopes to desktop computers like the 9825 and 9845 series.  HP made their own processors for most all of these products.  The early computers were based on the 16-bit Hybrid processor we talked about before.  At around the same time, in 1974, the HP LID realized they needed another processor, a control oriented processor that was programmable, and could be used to control the various hardware systems they were building.  This didn’t need to be a beast like the 16-bit Hybrids, but something simpler, inexpensive, and very fast, it would interface and control things like HPIB cards, printers, and the like.  The task of designing such a processor fell to Larry Bower.

The result was a Control Oriented Processor called the HP nanoprocessor.  Internally it was given the identifier 94332 (or 9-4332), not the most elegant name, but its what was on the original prototypes and die.   The goal was to use HP’s original 7-micron NMOS process (rather then the new 5-micron NMOS-II process) to help save costs and get it into production quickly.

Nanoprocessor Features – Note the speed has been ‘adjusted’

 

The original design goal was a 5MHz clock rate and instructions that would execute in 2 cycles (400ns).  The early datasheets have this crossed out and replaced with 4MHz and 500ns, yields at 5MHz must not have been high enough, and 4MHz was plenty.

Handwritten Block diagram

 

The Nanoprocessor is interesting as it is specifically NOT an arithmetic oriented processor, in fact, it doesn’t even support arithmetic.  It has 42 8-bit instructions, centered around control logic.  These are supported by 16 8-bit registers, an 8-bit Accumulator and an 11-bit Program Counter.  Interface to the external world is via an 11-bit address bus, 8-bit Data bus and a 7-bit ‘Direct Control’ bus which functions as an I/O bus.  The nanoprocessor supports both external vectored interrupts and subroutines.  The instructions support the ability to test, set and clear each bit in the accumulator, as well as comparisons, increments/decrements (both binary and BCD), and complements.

Here is one mask (Mask 5 of 6) for the prototype Nanoprocessor. You can see its simplicity.  On the bottom of the mask you can see the 11-bit address buffers and Program Counter

2.66MHz 1820-1691 – note the -5V Bias Voltage marked on it

The Nanoprocessor required a simple TTL clock, and 3 power supplies, a +12 and +5VDC for the logic and a -2VDC to -5VDC back gate bias voltage.  This bias voltage was dependent on manufacturing variables so was not always the same chip to chip (the goal would be -5VDC).  Each chip was tested the and voltage was hand written on the chip.  The voltage was then set by a single resistor on the PCB.  Swapping out a Nanoprocessor meant you needed to make sure this bias voltage was set correctly.

If you needed support for an ALU you could add one externally (likely with a pair of ‘181 series TTL).  Even with an external ALU the Nanoprocessor was very fast.   The projected cost of a Nanoprocessor in 1974 was $15 (or $22 with an ALU),  In late 1975 this was $18 for the 4MHz version  (1820-1692) and $13 for the slower 2.66MHz version (1820-1691).

At the time of its development in 1974-1975 the Motorola 6800 had just been announced. The 6800 was an 8-bit processor as well, made on a NMOS process, and had a maximum clock rate of 1MHz.  The initial cost of the 6800 was $360, dropping to $175, then $69 with the release of the 6502 from MOS.  By 1976 the 6800 was only $36, but this is still double what a Nanoprocessor cost

 

An early ‘slide deck’ (the paper version equivalent) from December 1974 sets out the What Why and How of the Nanoprocessor.  The total cost of its development was projected to be only $250,000 (around $1 million in 2020 USD).  The paper compares the performance of the Nanoprocessor to that of the 6800.  The comparisons are pretty amazing.

Interrupted Count Benchmark

For control processing interrupt response time is very important, the Nanoprocessor can handle interrupts in a max of 715ns, compare that to 12usec for the 6800.   The clock rate of the Nanoprocessor is 4 times faster but the efficiency of its interrupts and instructions are what really provides the difference here.

The clock rate difference (1MHz vs 4) really shows here, but the Nanoprocessor is also executed 3 times the instructions to do the same task, and still is faster.

Even using an external ALU compared to the Motorola’s internal ALU, the nanoprocessor is better then twice as fast (thanks here to its much higher clock frequency)

Full Handshake Data Transfer. Interfacing to the outside world was the main driver of the Nanoprocessor. Here we see that it can ‘talk’ to other devices much faster then the 6800

All instructions on the Nanoprocessor take 500ns to execute compared to the 1-10u for the 6800.

Today we do benchmarks based on framerates in games, or render times, but you can see that benchmarks were even important back then.  How fast a processor could handle things determined how fast the printer could be, or how fast it could handle external data coming in.  It’s no wonder that the Nanoprocessor continued to be made into the late 1980’s and many of them are still in use today running various HP equipment.

Nanoprocessor User Manual – October 1974

A big thank you to Larry Bower, the project lead and designer of the Nanoprocessor, who donated several prototypes, a complete mask set, and very early documentation on the Nanoprocessor (amongst some other goodies)

Documentation so ealy it has many hand written parts, and some corrections.  This had to be a very annoying oops if it wasn’t caught early on.  Even Engineers get their left and right mixed up on occasion

 

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News: New Server for CPU Shack http://www.cpushack.com/2020/07/08/news-new-server-for-cpu-shack/ http://www.cpushack.com/2020/07/08/news-new-server-for-cpu-shack/#respond Wed, 08 Jul 2020 17:50:19 +0000 http://www.cpushack.com/?p=23168 It took way longer then it should have but over the last 5 weeks CPUShack.com was transitioned to a new server.  We were hosted on a Media Temple GRID server, which got less and less suited for WordPress over the years so ended up with hundred of dollars in overages everytime i posted an article.  […]

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It took way longer then it should have but over the last 5 weeks CPUShack.com was transitioned to a new server.  We were hosted on a Media Temple GRID server, which got less and less suited for WordPress over the years so ended up with hundred of dollars in overages everytime i posted an article.  CPU Shack is now on a virtual dedicated server which should be faster and more flexible.  Next step will be to add SSL support, to keep up with current web guidelines.

If you notice anything not working, be sure to let me know.

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AMD Am29C327: How to Take a Picture of a Black Hole http://www.cpushack.com/2020/06/14/amd-am29c327-how-to-take-a-picture-of-a-black-hole/ http://www.cpushack.com/2020/06/14/amd-am29c327-how-to-take-a-picture-of-a-black-hole/#respond Sun, 14 Jun 2020 23:31:21 +0000 http://www.cpushack.com/?p=23156 Recently I came across one of the more unusual members of the AMD Am29300 series.  These were a set of processor elements (multipliers, FPUs, ALUS, registers) AMD designed to support AM29000 CPUs as well as for the bases for custom CPU designs.  Some. like the AM29C323 multiplier found common use in video game and other […]

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AMD AM29C327 Engineering Sample -1990

Recently I came across one of the more unusual members of the AMD Am29300 series.  These were a set of processor elements (multipliers, FPUs, ALUS, registers) AMD designed to support AM29000 CPUs as well as for the bases for custom CPU designs.  Some. like the AM29C323 multiplier found common use in video game and other applications.  Others like the AM29C325 32-bit FPU were used in educational experiments and research.  The 29300 (Bipolar) and 29C300 (CMOS) series are not particularly well known due to their obscure and often deeply specialized used.  At the top of the series lies the AMD AM29C327 Double precision (64-bit) FPU.  This FPU has a few tricks up its sleeves and is about as obscure in use as it gets….

The Am29C327 was on of the first chips made on AMDs CS-11A 1.2u processor (an enhancement of the 1.6u CS-11) .  It was first announced in 1987 with sampling to begin in late 1988.  The ‘327 contained over 250,000 transistors and was packed in a 169PGA package.  It is a IEEE754 compliant double precision FPU but also supports IBM and DEC formats.  It has 3 32-bit buses (2 for input and one for output) that, when multiplexed, allow for 64-bit maths.  Its little brother, the ‘325, only supports 32-bit math, and comes in a 145PGA package with around 30,000 transistors (11,000 gates).  So why does going to double precision involve nearly 10 times the transistor count?  It turns out that the ‘327 is more closely related to an actual CPU then a normal FPU.  The ‘325 has all of 8 instructions (add/sub, mult const subtraction and some conversions), while the ‘327 supports 58 instructions.  Of those 58 instructions 35 are Floating point, 1 is system management, and the other 22? Those are a full set of integer instructions.  The ‘327 actually supports more then just floating point.  Its internal ALU is a 64-bit 3 input design, allowing inputs from either the 2 external inputs, the output, a set of 8 64-bit registers, or a set of 6 constants.  Its instructions are 14 bits and it supports pipelining for even faster calculations.  Interestingly, pipelining can be disabled and the FPU will work in straight flow through mode.  So where is such a complicated chip used? Doing complicated math of course.

VLBA 25 Meter Antenna – NRAO

One such need for complicated math is in VLBI (Very-long-baseline interferometry).  VLBI is using a series of radio telescopes or antennas, spaced apart physically, to generate higher resolution data then a single antenna could.  The VLBA (Very-long-baseline array) is the largest of these, consisting of 10 25 meter radio telescopes spread across the USA.  The maximum distance between them is over 5500 miles, so with the right software and hardware, working together, they can emulate a single dish of several thousand miles diameter.  Production of this VLBA began in the late 1980’s and it went online in 1993.  One of the hardest parts of running a VLBA is correlating the data, data from each telescope must be precisely combined to generate the resulting observable output.  This is the job of the VLBA correlator, and as originally designed (and ran in such configuration at least into the 2000’s) this was based on a Motorola 68000 CPU driving multiple math cards.  These math cards (mainly responsible for FFT – Fast Fourier Transforms) were

M87 Black Hole – Imaged by Event Horizon Radio Array in 2017

managed by a single Dallas DS87C520 MCS-51 MCU that set up the data for a pair of AMD AM29C327 FPUs and a Xilinx FPGA to process.  A bit amazing that an 8-bit MCU was responsible for managing not one but two 64-bit FPUs, but in actuality all it had to do was route data to the proper places at the proper times, a gate keeper for the card.

Recently the VLBA, working together with other arrays to form the ‘Event Horizon,’ was able to take the very first ‘picture’ (radio data visualized) of an actual black hole.  Today’s arrays typically use modern CPUs, or even super computers (the LOFAR uses an IBM Blue Gene/P) to perform their correlation, this results in data output much quicker then the sometimes days it took the original VLBA to process data.  It all began with a 64-bit FPU from AMD in the 1980’s and scientists wanting to see what they could do.

 

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Chapter 2: Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997 http://www.cpushack.com/2020/05/13/chapter-2-mini-mainframe-at-home-the-story-of-a-6-cpu-server-from-1997/ http://www.cpushack.com/2020/05/13/chapter-2-mini-mainframe-at-home-the-story-of-a-6-cpu-server-from-1997/#comments Wed, 13 May 2020 21:04:10 +0000 http://www.cpushack.com/?p=23088 At the end of 2018, I started one project, which was called “Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997”. It was dedicated to the ALR Revolution 6×6 super server with six Intel Pentium Pro processors and a cost comparable to that of a brand new Ferrari in 1997. It took some […]

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At the end of 2018, I started one project, which was called “Mini-Mainframe at Home: The Story of a 6-CPU Server from 1997”. It was dedicated to the ALR Revolution 6×6 super server with six Intel Pentium Pro processors and a cost comparable to that of a brand new Ferrari in 1997. It took some 450 days and finally follows the continuation of the story, the super server received the long-awaited upgrade – six Intel Pentium II Overdrive 333 MHz Processors! For those years, such power was simply colossal, but how it compares with today’s and how much increased performance you will learn from this article.

I’ll admit 450 days is quite a long time, so I will briefly recall the contents of the previous series of the article.
And it all started like this: plunging into the world of mainframes and supercomputers , I wanted to try some super powerful system and the choice fell on the ALR Revolution 6×6 super server, which had six Socket 8 and supported up to 4 GB of RAM. For the late 90s, these were scary numbers, as well as its cost. One processor for such a system was estimated by Intel at $ 2675, and six were required, for one module of 256 MB of server memory it was necessary to pay $ 3500, and sixteen sticks were needed to get the coveted 4 GB of RAM.

A disk subsystem was also available with seven raid controllers and an 860 GB disk array, a twenty-kilogram power supply unit and the server itself … As a result, it was possible to reach amounts from 270 to 500 thousand dollars, and if you add here the inflation level over the years, these numbers will range from 435 to almost 800 thousand dollars. Now, in terms of performance, any low-cost computer will be faster than this monster, but the very fact of having such an opportunity in 2020, to feel the full power of that time, makes these large numbers insignificant, it is much more important to find and assemble such a monster.

ALR 6×6 Available Options

In the previous story, I studied performance with six Intel Pentium Pro processors with a frequency of 200 MHz and a 256 KB second-level cache and even overclocked all six copies to 240 MHz. As well as six top-end Intel Pentium Pro “black color” with a frequency of 200 MHz and a 1M L2 cache, which were able to overclock to 233 MHz. In my configuration, I had 2 GB of RAM standard FPM, 16 memory modules of 128 MB, which took over 4 minutes to initialize during the initial POST procedure.

Four gigabytes of RAM would bring this figure to 9 minutes, which is comparable to accelerating a train or taking off an airplane, although the latter can do it much faster. But then, having loaded at my disposal, six physical cores arrived at once, but without the support of MMX and especially SSE instructions.

Intel Pentium II Overdrive 333 MHz processor

The basis of any computer is the central processor. Intel Pentium Pro processors first appeared in 1995. Then there were the usual Pentiums without the Pro prefix, but this prefix in the name of the models said that these processors are positioned primarily as solutions for servers and workstations with their special Socket 8. The usual Intel Pentiums were installed in Socket 5 and 7. A significant difference between the Pro and the regular version of the Pentium desktop was the presence of a second-level cache in the Pro version, which, being on the same package, worked at the processor’s core frequency, thus allowing it to significantly increase performance.

For the various Intel Pentium Pro models, the L2 cache size ranged from 256 KB to 1 MB. Pentium Pro’s first level cache was 16 KB, of which 8 KB was for data and the same for instructions. For the subsequent Intel Pentium-IIs, the second-level cache worked at half the processor core frequency and amounted to 512 KB for all models, and it was located in the form of separate microcircuits on the cartridge at a distance from the CPU die itself. The L1 cache size was doubled in size to 32K, which offset the performance hit of the slower L2 cache.

Pentium Pro Slot 1 Slockets – Also made were Slot 2 versions.

The tested processors were produced at a 350 nm process technology. The number of transistors in the Pentium Pro totaled 5.5 million for the processor core itself and as many as 15.5 – 31 million were in the L2 cache memory, depending on its size. The L2 cache itself was located on a separate die near the CPU core. The processor had a free multiplier and the system bus frequency, depending on the model, was 60 or 66 MHz. Overclocking of the processor rested on overclocking the L2 cache, it the limiting factor.

CPU core on the right, L2 cache on the left

The Intel Pentium II Overdrive 333 MHz was a very interesting processor. This processor appeared, it can be said, thanks to the US Government, which funded a program to create supercomputers for modeling nuclear explosions and tracking the state of the country’s nuclear arsenal. The US government allocated funds for the construction of such a supercomputer, Intel won the tender and in 1997 handed over a turnkey supercomputer called “ASCI Red”.

ASCI Red consisted of 9298 200MHz Pentium Pro processors , all modules of the supercomputer were located in 85 rack cabinets. The total amount of RAM was 594 gigabytes, the disk subsystem consisted of 640 hard drives with a total disk space of 2 terabytes (consider now that this amount of storage is now provided by a single inexpensive hard drive). ASCI Red was the first supercomputer to break the line of 1000 GFLOPS or 1 teraflops. For several years in a row, it led the list of the TOP-500 fastest supercomputers in the world.

In 1999, modeling tasks became more complicated and the capacities of ASCI Red were already beginning to be lacking; an upgrade was needed. Programmers will always find a way to need more performance, no matter what you give them, especially if its for modeling the reliability of a strategic deterrent, or the weather, or…..  Intel won the tender again, and thanks to this event, a unique processor with a Socket 8 socket and the power of the Pentium II – Intel Pentium II OverDrive with a frequency of 333 MHz was born. The upgraded second-generation ASCI Red with 9632 processors after the upgrade provided 2.38 TFLOPS performance in the Linpack benchmark. Such high-quality characteristics allowed ASCI Red to hold the title of the fastest supercomputer until June 2000.

The Intel Pentium II OverDrive, which was the final stage in the evolution of Socket 8, belonged to the sixth generation of Intel processors (P6). The processor was announced in August 1998, despite its specificity, the recommended cost of the processor in batches of 1000 pieces was $ 599. Physically, this processor was installed in Socket 8, however, in fact, we see “Deschutes” core Pentium II , supplemented by a 512-kilobyte L2 cache operating at the processor core frequency, unlike the normal Deschutes core PIIs.  These are the only Pentium II processors (excluding the Celerons of course which had a on die cache and the Mobile Dixon core which had 256k of fullspeed cache) with a full speed L2 Cache. The Pentium II OverDrive VRM was integrated into the Pentium II OD module and lowered the supplied voltage from the motherboard (3.1-3.3V) to the required 2 volts for the PII core.

Pentium II Overdrive Module with Heatsink removed. CPU die is on the left and 512K of Cache on the right

The processor multiplier is locked at 5x, which with a 66.6 MHz FSB gives a total of 333 MHz. There are two versions of this processor, the first with SPEC – SL2KE, which is equipped with an active cooling system and SL3EA with a passive one. But the biggest plus is not only the increased processor clock speed, but also the support of the MMX instruction set and some others.

Since the motherboard supports multiplier changes up to x5.5, which would result in 366 MHz, I at the same time studied the properties of engineering samples of the Intel Pentium II Overdrive 333 MHz with SPEC Q0125. As the owner of such a processor told me, even the multiplier for this Engineering Sample is locked. Maybe it’s for the better, since acquiring six of these ES processors will be comparable to buying any top-end modern CPU, but first you need to find them somewhere else in such quantity.

Mendocino

It would seem that I spent more than a year to find and purchase six Intel Pentium II Overdrive 333 MHz processors, which now sell for an average of $ 200 at the world-famous flea market (Ebay.com), and got the maximum ALR Revolution 6×6 config, but as always there is no limit to perfection. But more about that below.

Mendocino is the name of the core of Celeron processors manufactured since 1998 in the performance of SEPP (Slot1) and PPGA (Socket 370). In 1999, Intel abandoned the Slot 1 form factor in favor of the familiar PPGA. Plastic Celeron processors were cheaper to manufacture, manufactured using 250 nm technology and had a built-in 128 KB L2 cache running at full processor core speed. The frequency range ranged from 300 to 533 MHz.

PPGA Celeron Processor – Full speed 128K of cache

And where does the Celeron Mendocino fit? The fact is that it is possible to launch Celeron processors in SMP (Symmetric Multiple Processor) and enthusiasts have been doing this for quite some time. Celeron at its core has the core of a full-fledged Pentium II, which, as you know, supports SMP. The difference between these processors is only in the L2 cache, Celeron L2 = 128 Kb, but the frequency can reach higher values of 533 MHz versus 450 for Pentium II.

Support for SMP is the presence of the BR # 1 signal, which is physically present in the processor itself, but has not been routed on the motherboard. Once this secret was discovered, the solution to the SMP problem was not long in coming. Enthusiasts picked up a soldering iron, and motherboards manufacturers ABIT and QDI, which were inspired by this idea, even released their serial products. Suffice it to recall the ABIT BP6 motherboard based on the Intel 440BX chipset with two Socket 370. (Editor’s Note: Oh the Days of running my BP6 with dual Celeron 366s happily running at 550MHz, Intel was not amused, but I was)

Further, there is one adapter from the company Powerleap model PL-ProII, which just allows you to install Intel Socket 370 Celeron processors  in Socket 8 motherboards, they are that closely related.

Therefore, it is theoretically possible to install six Intel 533MHz Celerons, which in total will give us 3200 MHz. Of course, I don’t know if all six processors will work, but the chance is not bad =) How much I did not surf the Internet, but I did not find the implementation of such bizarre ideas. I can find six Celerons without difficulty, but six Powerleap PL-ProIIs are unlikely. I had one such adapter, but I had to sell it in order to implement this project, as well as part of my other exhibits (( Therefore, if someone has one, or they know where to find it for responsible money, write to me in the discussion of this article or to my e-mail: max1024@tut.by (perhaps they could be recreated?)

We continue to fantasize LOL. In turn, if you expand even further the boundaries of imagination, and install another adapter with support for Pentium III processors with the Tualatin core in the Powerleap adapter, then who knows what can happen at all in the output, maybe such a sandwich….

The idea turned out to be interesting, so I do not give up hope that the next part or continuation of this story will someday be published. Perhaps in 2025.

Windows Vista Server

Having now at our disposal six Intel Pentium II Overdrive 333 MHz, which have already acquired support for MMX instructions and have risen one more stage of evolution along the processor ladder, I wanted to try to install an even more modern operating system.

Let me remind you, the last time I was able to install an operating system that was different from the recommended ones: Microsoft Windows NT Server 4.0 Enterprise, Microsoft Windows 2000 Advanced / Datacenter Server, which fully prevent you from running programs and tests written for the beloved Windows XP. As a result of lengthy experiments, we got such an OS: “Windows .Net Enterprise Server. Build 2600 Service Pack 2 ”, which is a semblance of a server operating system with a Windows XP kernel.

This time I wanted to raise the bar even higher and aimed at the family of operating systems based on the Windows Vista kernel. The ideal option was Windows Server 2008 Enterprise Edition (x86), but at first I decided to try installing Windows Server 2003 Enterprise Edition. Although it was written on paper about a hardware error in the core of the CPU of the Intel Pentium Pro family of processors and earlier Pentium II’s and the related problem of memory “leak” and the inability to work in the SMP mode of the above processors, I decided to check this in practice.

The result of this experiment is predictable – six Intel Pentium II Overdrive 333 MHz will not work as part of the ALR Revolution 6×6 running the Windows Server 2003 family of operating systems. Only one CPU is visible. And it’s a pity, this is how one hardware error puts an end to the happy future of such interesting processors.

The next step was to install Windows Server 2008 Enterprise Edition. For many parameters of the minimum configuration, ALR Revolution 6×6 met those requirements needed for the successful installation of this operating system. The installation process began safely, files began to be copied from the DVD-ROM’a to the SSD.

But after reboot I saw a window like this:

Again ACPI rears its ugly head … Saying that my config almost met all the minimum requirements, I did not mention that starting from Windows Vista all the kernels of this and subsequent operating systems are ACPI compatible, in other words, nothing will work without hardware ACPI. And the answer here lies in the BIOS of the  ALR Revolution 6×6, which was released long before the advent of ACPI.

But still there is a chance of installation, but this requires intervention in the BIOS code, but unfortunately I still can’t get a BIOS programmer. Back in the days of Socket 7, when the first revision of ACPI began to appear, motherboard manufacturers released new versions of their BIOS with support for this technology. I went through this as an example of an Asus P5A motherboard on the Ali ALADDiN V chipset for Socket 7 processors, when the ACPI BIOS Revision 1006 was released. This made it possible to install Microsoft Windows 7 x86 on this motherboard with an AMD K6-2+ processor.

An alternative solution to this problem was to look for early builds of Windows Vista Server. The initial project of this development was called “Longhorn”.

The image of this OS was found on the Internet (of course), burned to DVD and the installation process begin:

Everything went as usual, the files were copied, but upon completion of the copying process and reboot, the same error with ACPI was waiting for me.

Again, having spent a fair amount of time, I decided that I would start searching for the kernel of an operating system without ACPI support in earlier versions of Windows Vista or the Longhorn project. Perhaps they exist. If any early build is installed, then it will be easier with the implementation of SMP support. I tried different builds: 4042, 5098, as well as beta’s of the 2nd version. It should have turned out like this:

But the success of this event still ended with ACPI support from my test system. All tested builds still required ACPI support. As a result, I put this idea into a long drawer and decided to conduct all the tests on a proven Windows XP-like OS, where six Intel Pentium Pros felt great. To solve this problem, one head is not enough, so valuable ideas can be written in the discussion of this article, do not be shy 😉

Test system and test results

The test bench will include processors:
• 6x Pentium II Overdrive 333MHz L2=512 Kb
• 6x Pentium Pro 200MHz L2=1024 Kb
• 6x Pentium Pro 200MHz L2=256 Kb

Motherboard:
• Unisys Aquanta HS6 (10140) chipset «Intel 450GX» (6x Socket 8);

Video card:
• PNY GeForce2 MX400 PCI 64Mb (Forceware 93.21);

SSD:
• Kingston SSDNow V300 (60 Gb).

Performance testing was carried out in the “Windows Whistler .Net Advanced Enterprise Server, Build 2600, Service Pack 2, 3 in 1” author’s edition using the following software:
• Super Pi mod. 1.5XS (1M task)
• PiFast v.4.1
• wPrime v.1.43
• HWBOT Prime v.0.8.3
• CPU-Z v.1.87.0
• WinRAR x86 v. 5.40
• 7-Zip v.16.04
• AIDA64 5.50.3600
• SiSoftware Sandra 2004 SP2
• Cinebench 2003
• Cinebench R10

Tests

To start, a couple of single-threaded tests: Super Pi (1M task) and PiFast.

Super Pi mod. 1.5XS (1M task)
Minutes (less is better)

If we compare the performance of the fastest Pentium Pro with a clock frequency of 200 MHz and a 1M L2 cache then replacing one Pentium II Overdrive 333 MHz gives an additional one third of the performance. And if the number of such processors is the same as in ASCI Red – 9632 pcs., Then it turns out almost 3 million percent, if I calculated everything correctly.  You can see that the L2 cache size helps some but mostly this is a pure clock speed/architecture test.

PiFast v.4.1
Seconds (less is better)

In this test, the previous performance growth dynamics between the Pentium Pro and Pentium II Overdrive are preserved. Although this test loves the processor clock speed more than the cache size, even so, the overdrive gap from the 400 MHz Celeron turned out to be not very large. I really want to install six such Celerons in this system.

wPrime v.1.43

The first test that supports multithreading. For this article, I decided to measure the performance of not only six Intel Pentium II Overdrive’s, but also see what five and four processors are capable of, since the system allows even odd configurations to be used and scales well.

Seconds (less is better)

The performance criterion turned out to be six to four, the performance of six Pentium Pros corresponds to four Pentium II Overdrive, more precisely, overclocking Pentium Pro up to 233 MHz. Six “overdrives” have come off enough to match the performance of four server Xeon clocked at 400 MHz, or their performance is equal to one AMD Athlon XP with a PR rating of 2100+ and a frequency of 1733 MHz, released in early 2002. It took a little less than four years  for an ‘ordinary’ processor to match the performance of the 6x Overdrives.

Also of note adding a CPU (from 5 to 6 Overdrives) results in a very linear performance increase.  The ALR has very little overhead in handling the addition of processors.

HWBOT Prime v.0.8.3
Total score (more is better)

If in the past, the performance of a pair of gigahertz Intel Pentium III Xeon was something fantastic, now, 6 overdrive even managed to outperform this pair A slightly overclocked (by 5%) representative of a 64-bit new school – AMD Athlon 64 3800+ on Socket 939 is only slightly faster  despite the technological abyss between them.  Adding processors here resulted in less gains then in wPrime.

WinRAR x86 v. 5.40;
Kb/s (more is better)

The memory subsystem from the upgrade has not changed, all of the 66 MHz Fast Page Mode memory is used, but the numbers nevertheless increased due to brute processor power.

7-Zip v.16.04 (dictionary size 32 Mb);
Total score in MIPS (more is better)

Here again we see the effect of 6 to 4 or parity in the performance of 4 “overdrive” to six Pentium Pros. The slower memory subsystem interferes with archiving with more modern opponents, if it could be overclocked to 75 MHz …perhaps in the future.

AIDA64 5.50.3600
I present to you the results in this test package of six Intel Pentium II Overdrive 333 MHz.

And my favorite test is Cache and Memory Benchmark. See how the speed of the caches of both processors has increased. From left to right: Pentium II Overdrive 333 MHz and Pentium Pro 200 MHz (L2 = 1024 Kb).  Interestingly the L2 Cache write speed is nearly 25% faster on the original Pentium Pro, similarly its latency is better as well.

AIDA64 5.50.3600
CPU Queen, score (more is better)

The 6x Overdrives beat a 2.8GHz Pentium 4.  The P6 architecture was faster then the Netburst resulting in clock for clock performance gains.

AIDA64 5.50.3600
FPU Julia, score (more is better)

AIDA64 5.50.3600
FPU VP8, score (more is better)

Both of these FPU tests are less dependent on multiple cores, significantly impacting the ALRs score.  The Pentium III FPU also was greatly enhanced (with the addition of SSE amongst other things) which is readily apparent here as both the VP8 and Julia tests are heavily optimized for these

SiSoftware Sandra 2004 SP2
Arithmetic benchmark, MIPS (more is better)

SiSoftware Sandra 2004 SP2
Multi-media benchmark, it/s (more is better)

At least in the Integer test the 6x Pentium II Overdrives do well, the Multimedia test, being more FPU heavy, favors the PIII core, but at least we can say we beat an a quad Itanium?

Now we get to the most popular multi-threading number of crushing tests – Cinebench!
Cinebench 2003
points (more is better)

To the question, how many cores and which are better for rendering. There is a Pentium III-S 1400 MHz behind the Tualatin-S core, Socket 370, which is nearly as fast as the ALR The dual Sot 1 Intel Pentium III EB 933 MHz are quite a bit faster.  Clock speed (total available clock speed) as well as architecture matter a lot here.  Though you can easily see the weakness of the P4 core.

Cinebench R10
points (more is better)

 

Interesting numbers, isn’t it? You can try to find this test and look at your result. The final rendering of the previous system with six one-megabyte Pentium Pro with a frequency of 200 MHz was completed in 21 minutes and 14 seconds. Overclocked six cores to 233 MHz reduced this time to 18 minutes and 13 seconds, and for six Pentium II OverDrive it took 13 minutes and 32 seconds. The advantage is 4 minutes 41 seconds, and if we multiply this time by the entire number of processors in the ASCI Red supercomputer, we get 31 days full time 24/7 or 1/12 of a year of time savings, and this is already a tangible figure.

In the last article, I compared the six Pentium Pros in this test with the Intel Core i7-7800X, which rendered the final image in 20 seconds. This time it became interesting to me, and in how many seconds will the modern TOP from Intel – Core i9-10980XE be able to do this? I found a man, who owns this processor and he agreed to help me with the numbers and completed the tests. Now you can find out these final figures. So, with the default settings, the test was completed in 11 seconds, and when overclocking all 18 cores to 5 GHz in nine! And although the Cinebench R10 supports only 16 threads, you can still imagine the difference when you had to wait for a few hours on the desktop PC and literally a few seconds now to complete the same task.

And in the form of a small bonus, I will give the results of the integrated CPU-Z test:

Conclusion

It is time to make a conclusion. No doubt the ALR Revolution 6×6 and similar systems are fantastic. It’s even interesting to use such a machine at home. On one processor, you can hang the server of some network game C&C, StarCraft or Counter-Strike, for example, on the other the client of this game will be launched, on the third second, on the fourth will play mp3 in Winamp and there will still be a couple of free kernels that you can always something to load in the background. Two or four gigabytes of RAM should be more than enough for these and other tasks.

So far I have only one problem, what should take up 8 free PCI slots? Ha-ha )

For its time, such performance was unattainable for most organizations because of the ultimate cost of such systems. But the most interesting thing is that since the late 90s of the last century, progress has been rapidly gaining momentum and literally after 4-5 years, single-core processors for home use, costing hundreds of times cheaper, skipped this monster.

What we have now is not necessary to explain. The progress in the past 7 years has slowed significantly, however, since the “return” of AMD to the people with the brand name “Ryzen” and the corporate “Epyc” the process has revived significantly. And for this we cannot but rejoice. Perhaps in a couple of years the Cinebench R10 test will be executed on the nex gen (no no not THAT NexGen) processor in 1 second, then we can assume that the future has already come =)

I don’t want to put an end to this experiment, as long as there is room for striving, I will try to implement it, although it becomes more and more difficult every year, but I’ll come up with something…There is yet the possibility of faster RAM, overclocked Overdrives, or the elusive 6-way Celerons, or perhaps ACPI compliant BIOS.

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DEC M7260 KD11-A CPU: The PDP-11 Goes MSI http://www.cpushack.com/2020/04/16/dec-m7260-kd11-a-cpu-the-pdp-11-goes-msi/ http://www.cpushack.com/2020/04/16/dec-m7260-kd11-a-cpu-the-pdp-11-goes-msi/#respond Fri, 17 Apr 2020 05:52:02 +0000 http://www.cpushack.com/?p=23078 Back in 1972 DEC released the ‘budget’ PDP-11/05 16-bit computer.  The original PDP-11/20 had been released 3 years before and its CPU (the KA11) was based on simple TTL, its ALU could perform adds and that was all, which meant its designers had to get creative in implementing the instruction set.  By 1972 however things […]

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PDP-11/05 Front Panel (pic from vintage_electron)

Back in 1972 DEC released the ‘budget’ PDP-11/05 16-bit computer.  The original PDP-11/20 had been released 3 years before and its CPU (the KA11) was based on simple TTL, its ALU could perform adds and that was all, which meant its designers had to get creative in implementing the instruction set.  By 1972 however things had changed, there still was no 16-bit processors available but there was now single chip 4-bit ALU’s.  The ALU was the famous 74181 and formed the heart of the KD11-A, DEC’s 4th processor design (the ‘third’ was the KB11-A which was similar but based on the faster 74S181 and used in the PDP-11/45 and released at the same time) .

The KD11-A consisted of a pair of boards, the M7260 Data Path Module and the M7261 Control Logic and Microprogram Module.  All the processor functional components are contained on these modules. The M7260 Data Path Module contains: data path logic, processor status word logic, auxiliary arithmetic logic unit control, instruction register and decoding logic, and serial communications line interface. The M7261 Control Logic and Microprogram Module contains: internal address detecting logic, stack control logic, Unibus control logic, priority arbitration logic, Unibus drivers and receivers, microbranch logic, microprogram counter, control store logic, power fail logic, line clock, and processor clock.   The M7260 was he brain, and the M7261 told it what to do, containing the microcode to implement the PDP-11 instruction set.  This was the first version (with the 11/45) of the PDP-11 that was microcoded.

Fairchild 934159 74181 MSI 4-bit ALU made on a Bipolar – This example from very early 1971

The KD11-A ran off a single 150ns clock resulting in a raw clock speed of 6.67MHz, however performance was limited by memory access speed. The PDP-11/05 supported up to 32K Words (64KB) of core memory and this memory could only run at a 980ns cycle time.  This limited the 11/05 performance to around 1MHz.  This was still quite good for 1972!.

The 74181 was capable of running at 42MHz (and 90MHz for the 74S181 Schottky TTL versions) but in a set of 4 this drops to about 27MHz (with the carry generator taking some time).   Speed, however, is usually limited by other things rather then the ALU itself.   The 74181 ALU contains the equivalent of 62 logic gates (170 transistors) and can perform 16 different arithmetic and logic functions on a pair of 4-bit inputs.  Ken Shirriff did an excellent die level analysis of a ‘181 thats worth reading.  It includes pretty pictures even.

DEC M7260 – Data Path for the KD11-B CPU – Dated July 1972

This particular KD11-A board is one of the very first made.  It is dated July 20th 1972, a month after the initial release of the 11/05.  The big white chip is a General Instruments AY-5-1012 UART.  To its right you can see thr 4 74181 ALUs.  Each is 4-bit and together they form a complete 16-bit ALU for the CPU. A 74150 Multiplexer helps determine what data goes where.  The 74182 is the Look ahead carry generator for the ‘181’s.  Most of the rest of the chips on the board are ROMs and supporting logic.  There is also 4 Intel C3101A 35ns SRAM chips, these are 16×4 SRAMs used as scratch pad memories and only were used in the very first version of the CPU (later versions replaced them with cheaper 7489 TTL versions).  The Scratch Pad Memory is what forms the registers for the CPU.  There are 16 16-bit registers with the the first 6, R0-R5 being general purpose registers and the rest special purpose such as the Program Counter, Interrupt Vector, etc.

M7261 Control module – Contains the microcode for the CPU (pic from xlat.livejournal.com)

Another interesting point on this board is the very large amount of green wires running on the board.  These are called ECO wires, which are ‘Engineering Change Order’ wires, and are placed, by hand, after the board is made to correct faults in the board layout.  The goal is to not have these as they are expensive and delicate and can result in failures down the road, so further revisions of the board would have these fixed/implemented in the PCB.  You do not see these much at all any more as modern design/testing tools virtually eliminate the possibility of a faulty PCB layout making it into production.

When it was released the ~1MHz 11/05 cost $25,000, which in 2020 US Dollars is around $154,000.  THe PDP-11 series ended up being one of the most popular minicomputers, selling over 600,000 units over the years.  Later versions like the LSI-11 series moved the entire CPU to a single LSI chip, adding Extended Instructions, Floating Point Instructions, faster memories and other performance enhancements well into the 1980’s.   It was also widely comied, and enhanced in the Soviet Union and Russia.  It was on a Soviet PDP-11 clone that Tetris was developed, a game we are all rather familiar with.

Its amazing to see where computers have come in the span of but a few decades. but these important parts of history continue to be used.  Perhaps not the 11/05, but there are many PDP-11 systems still working away, typically inindustrial environments, ironically helping produce things likely far more advanced then themselves.

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The Intel N60066: Unwrapping a Mystery http://www.cpushack.com/2020/03/20/the-intel-n60066-unwrapping-a-mystery/ http://www.cpushack.com/2020/03/20/the-intel-n60066-unwrapping-a-mystery/#respond Fri, 20 Mar 2020 23:57:50 +0000 http://www.cpushack.com/?p=23057 One day last summer, I was browsing the deep dark corners for processors, a fun, yet dangerous activity.  I happened upon a lot of PCBs from some older industrial automation equipment.  No real information was provided (those buying these boards clearly would already know what they needed).  They did however have a RTC, an EPROM […]

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Fischer & Porter 53MC5 – The beginning of the Mystery

One day last summer, I was browsing the deep dark corners for processors, a fun, yet dangerous activity.  I happened upon a lot of PCBs from some older industrial automation equipment.  No real information was provided (those buying these boards clearly would already know what they needed).  They did however have a RTC, an EPROM a 16MHz crystal, and a large 84-pin PLCC.  That PLCC was marked as an Intel N60066.  Seeing such a large chip, surrounded by such components almost always means its some sort of processor or microcontroller.  The problem is, there is no known Intel 60066 part.  The chips were all made in the late 80’s and early 90’s and had  1980 and 1985 copyrights.  A 1980 copyright typically screams MCS-51, as that was when it was introduced and nearly all such chips bear an Intel 1980 mark.

Intel N60066

The boards themselves were dated from 1990 all the way to the early 2000’s (I bought a lot of them, another problem I have).  Some had the part number 53MC5 and the logo of Fischer & Porter.  Fischer & Porter has existed since the 1930’s and was a leader in instrumentation.  They were bought by Elsag Bailey Process Automation (EBPA) in 1994 which itself was swallowed up by ABB in 1999.  The boards design was largely unchanged through all of these transitions. Searching for documentation on the 53MC5 part number (its a Loop Controller) didn’t yield details on what the N60066 was unfortunately.  The only thing left to do was to set it on fire…

Unfortunately this is the only way I currently have for opening plastic IC’s (I need to get some DMSO to try apparently).  After some careful work with the torch and some rough cleaning of the resulting die it was readily apparent that this was an MCU of some sort.  The die itself was marked… 1989 60066.  This wasn’t a custom marked standard product, this was a custom product by Intel for this application, a very surprising thing indeed.  Unlike other companies such as Motorola, Intel was not well known for custom designs/ASICs.  This wasn’t their market or business plan.  Intel made products to suit the needs they saw, if that worked for the end user, great, if not, perhaps you could look elsewhere.  They would gladly modify specs/testing of EXISTING parts, such as wider voltage ranges, or different timings, but a complete custom product? Nope, go talk to an ASIC design house.  Its likely Fischer & Porter ordered enough of these to make it worth Intel’s effort.

Knowing this was an MCU and suspecting a MCS-51 further searching revealed the answer, and it came from the most unusual of places.  In 2009 the US NRC (Nuclear Regulatory Commission) determined there was no adequate Probabilistic Risk Assessment (PRA) for Digital systems in their agency, so set about determining how best to calculate risk of digitally controlled systems.  They analyzed a system used to control feedwater in nuclear reactors.  These are critical systems responsible for making sure the reactor is kept with the right amount of cooling water at the right time, failure of course is not an option.  The 53MC5 is what is used for controlling the valves.  In this document we find this nugget:

The controller is an 8051 processor on board an application-specific integrated circuit (ASIC) chip that performs a variety of functions.

Well that certainly helps, it is indeed a custom ASIC based on an 8051.  The report also provided a diagram showing the ASIC system.  This is an 8051 core with RAM/ROM (normal) as well as a Watchdog timer, a PAL, I/O Buffers, and Address Logic.

I sent a couple of these chips to my friend Antoine in France for a proper die shot, which he is quite amazing at.

Intel N60066 die – 8051 core on the left. Die shot by Antoine Bercovici

The 8051 core is on the left of the die, with its RAM/ROM.  A very large PLA occupies the bottom right side of the day.  In the upper right is presumably the external watchdog timer for the ASIC.  The lines crossing the die mostly vertically are a top metal layer used for connecting all the various sections.

The hunt for a new CPU/MCU is part of the thrill of collecting.  The satisfaction of finding out what a mystery chip is can be worth many hours of dead ends in researching it.  Its not common to have to go to the NRC to find the answer though.

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ESA Solar Orbiter: When SPARCs Fly http://www.cpushack.com/2020/02/09/esa-solar-orbiter-when-sparcs-fly/ http://www.cpushack.com/2020/02/09/esa-solar-orbiter-when-sparcs-fly/#comments Sun, 09 Feb 2020 23:58:20 +0000 http://www.cpushack.com/?p=23039 In a few hours (assuming no more delays, UPDATE: Launch Successful) the joint NASA/ESA Solar Orbiter mission will launch on a ULA Atlas 5 Rocket out of Florida, USA.  This is a mission a long time coming for the ESA, which like NASA has to get its funding from the government, except in the case […]

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ESA ERC-32SC

ERC-32SC – SPARC V7 MCM with RAM and MIL-STD-1553

In a few hours (assuming no more delays, UPDATE: Launch Successful) the joint NASA/ESA Solar Orbiter mission will launch on a ULA Atlas 5 Rocket out of Florida, USA.  This is a mission a long time coming for the ESA, which like NASA has to get its funding from the government, except in the case of ESA, that involves the governments of many countries in the EU, which can make planning a bit more tricky.  The mission was originally baselined in 2011 and hoped to launch in…2013…then 2017..then 2018 and finally a launch date in 2020.  The original proposal dates to the late 1990’s as a mission to replace the joint NASA/ESA SOHO Solar mission that had launched in 1995.  This creates some interesting design choices for a mission, as designing often happens before a mission is completely approved/funded.  For Solar Orbiter this is one of the main reasons for it being powered by a computer that by today’s standards is rather dated, space standards no less!

Solar Orbiter – ESA

The Solar Orbiter is powered by a processor designed by the ESA, the ERC-32SC.  This is the first generation of processors designed by the ESA.  It is a SPARC V7 compliant processor running at 25MHz and capable of 20MIPS.  The ERC-32SC is a single chip version of the original ERC-32 which was a MCM (Multi chip Module) containing 3 dies that made up the processor (the Atmel/Temic TSC691 Integer Unit TSC692 FPU and TSC693 Memory Controller) that was made on a 0.8u CMOS process.  The Single chip version was made possible by a processes shrink to 0.5u.  It was also made by Atmel,  (whom acquired Temic) and is commercially known as the TSC695 as it is designed for space use, is capable of handling a 300krad Total Ionizing Dose of radiation.  The computer used in the Solar Orbiter was built by RUAG and has two seperate ERC-32SC processor systems for redundancy.  Each of the ERC-32SCs are actually mounted on a MCM, the single chip SPARC, 48MB of DRAM (38 of which is used, the remainder is for Error Detection/Correction via Reed Solomon method), and a MIL-STD-1553 bus controller/RTC/IO are included in the package.

Fujitsu MB86900 – Original SPARC V7 Processor from 1987

The original specifications for this processor were developed back in the 1990’s, which is why it is a SPARC V7, equivalent to the very first Sun SPARC workstations of the late 1980’s powered by the likes of the Fujitsu MB86900/MB86901.  The ESA has developed several follow on processors since, all based on the later SPARC V8 architecture.  They are faster, and more efficient then the ERC-32SC, with some even being dual core processors.  They are known as the LEON-2 and the later LEON-3.  LEON2 has a 5-stage pipeline and no SMP support, while LEON3 increases the pipeline to 7-stages and adds SMP support.  LEON3 is also a VHDL core able to be added to many ASICS/FPGAs (LEON2 is a hard core).  The Solar Orbiter also has both LEON2 and LEON3 processors on board as well…

The Solar Orbiter caries with is 10 different scientific instruments, and each of them has their own processing subsystem, 9 of which are powered by LEON SPARC processors.  Its common for the main processor of a spacecraft to be the most powerful, but in this case the instruments each possess their own processor more powerful then that of the main spacecraft computer.   This is in large part due to many of these instruments being designed well after the original spacecraft bus and systems were baselined.  Payloads can be added/changed much later in the design of the spacecraft allowing their designers to use more modern computers.

Instrument Processor(s) Notes
Solar Orbiter OBC ERC-32SC – Atmel TSC695 Spacecraft Platform Processor
SoloHi LEON3FT – Microsemi RTAX2000 FPGA
MAG-IBS/OBS LEON3FT – Microsemi RTAX2000 FPGA
RPW-SCM/ANT LEON3FT – Microsemi RTAX4000D FPGA
LEON3FT – Cobham UT699
Two processors
SWA-HIS/EAS/PAS LEON2FT – Atmel AT697F up to 100MHz
EPD-SIS LEON2FT – IP Core
STIX LEON3FT – Microsemi RTAX2000 FPGA
EUI LEON3FT – Cobham UT699 66MHz Single core
METIS LEON2FT – Atmel AT697F
PHI LEON3FT – Cobham GR712RC Dual core up to 100MHz
SPICE 8051 + FPGA Long live the MCS-51

There is also likely more processors on this mission as well, but it can be hard to track them all down, nearly every system has its own processing (star trackers, radios/ attitude control etc)

So as you watch the launch tonight, and perhaps see science/pictures from the Solar Orbiter (or just benefit from its added help in predicting solar storms and allowing us here on Earth to prepare for them better) think of all the SPARCs it has taken to make it function.

 

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