Teranex Piranha TN3260B – 1024 PE Array @ 64-90MHz

The GAPP (Geometric Arithmetic Parallel Processor) was designed in 1981 at Martin Marietta, which later became Lockheed Martin Electronics & Missiles.  It was funding in large part by the US Dept. of Defense as a way to develop technologies for ultra high-speed image processing.  There was a strong need for image processing, in near real time for military applications, in particular pattern recognition.  Being able to process a moving image and match its features to known patterns was very useful for targeting of many weapons system.

The GAPP processor was a massively parallel SIMD (Single Instruction Multiple Data) processor.  SIMD works very well on large sets of data that are processed in the same way.  In the design of GAPP, this data set was the 2D-array of an image, or frame, from a video.  The GAPP is at its core a very large array of simple processors, called processor elements (PE).  Each PE is relatively simple, containing a single bit ALU and registers/memory.  Each PE handles a single pixel of the image/frame, and is connected in a 2-D mesh to its 4 nearest neighbors.  This allows arrays of these PE’s to scale very well.  By 1992 Lockheed had GAPP systems with 82,944 elements and by the 2000’s systems were available with nearly 300,000.

In 1998 TeraNex was formed to commercialize this technology, and in 1998 there was a looming problem in television, one that the GAPP, and newly formed TeraNex were well suited to solve.

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6801/6803 Expansion Board and PCP

After several months of development an expansion for the 680x/650x Test system is now available to support the very popular and widely used 6801 and 6803 MCUs.  The Motorola 6801 was one of the first (with the 6802) MCU’s that Motorola made based on the MC6800 8-bit processor.  It includes RAM/ROM, Serial I/O and timers.  The test board tests the function of the base CPU, the timers/data capture, and the Serial I/O.  The MC6803 is a 6801 without the built-in ROM and with less I/O.

The expansion supports both types as well as their copies/derivatives made by Hitachi, Fujitsu, SGS and others.  The expansion is included in the complete 680x/650x Test system, bringing its total supported processors to well over 35.  The expansion does require updated firmware, which is included in all new systems (and available to upgrade previously sold systems.)

Matrox SX-900: Serial# 266 – Nov 1984

In today’s age of GPU’s the GPU is often used to offload the x86 processor.  Many tasks are well suited for the thousands of GPU cores on modern graphics cards, tasks that would be a large burden on an x86 processor.  In 1984 though, Matrox took a different approach to high-end GPU design.  Matrox was founded in Canada in 1976, and has been making graphics cards since they first released the S-100 bus ALT-256 in 1978.  Matrox kept up with the hardware changes of the time, released MULTIBUS boards, Q-Bus boards, and eventually PC compatible cards.

The SX-900 was the value (around $2000) version of their 2 board GXB-1000 (that was $3000-4000).  The Matrox SX-900 was a standard MULTIBUS card with support for 640x480x8bit graphics.  It supported a fill rate of 20 MPixels/sec which was very impressive in 1984.  By comparison, the Nvidia NV1 (STG-2000) released in 1995, was only capable of a 12MPixel/sec fill rate, albeit at a richer color depth.  So how did Matrox, in 1984, achieve such performance?

Matrox SX-900: Powered by a 80286-4 Processor and upD7220 Graphics Primitives Processor

Matrox used an Intel 80286 processor, running at 4MHz (the slowest 286 made) as a Display List Processor.  It handles all high level commands (256+) and then controls the rest of the cards hardware, including the NEC uPD7220 Graphics primitive processor and a advanced pixel processor (implemented in PALs/TTL).  Together they bring rather impressive performance.  The board supports up to 4096 colors (in a Lookup Table) but can only display 16 at a time. Interestingly the board has 512K of 150ns DRAM for use as video memory, more than enough for 640×480 graphics.  Also included is 640 bytes of 25ns ECL SRAM (5x AM9122-25PC), and 16K of 120ns CMOS SRAM implemented with 2 HM6264s.  Firmware (the same firmware used for the GXB-1000) is held in 4 27128 EPROMs for simple updating as needed.

The SX-900 was used in CAD systems, industrial automation, processor control, and other applications where data needed to be shown the user graphically, rather then on a green glowing monochrome text display.  One of the more famous applications was the University of Milan (in Italy) where the SX-900 (supported by Intel iSBC286 computing boards) controlled the K800 Superconducting Cyclotron, a 100MeV particle accelerator.  THis cyclotron ended up being moved and completed at Catania, also in Italy.

Many of these boards are still in use, dutifully displaying graphics and providing user interfaces to thousands of processor control systems in factories and institutions around the world.

HP A600+ Processor Board. 4x AMD AM2901CDC (1820-3117) 1x AMD AM2904DC and 1x AMD AM2910 (1820-2378). Some versions used 2901’s from National Semiconductor.

In the early 1960’s HP was exploring connecting computers to its various instruments, for control, monitoring, and logging.  The DEC PDP-8 had come out in 1965 as perhaps the first mini-computer and could be used to control HP’s instrument’s.  However, HP determined that it would actually be easier, and faster to design and build their own computers rather than work with DEC.  DEC probably didn’t see HP’s interest as important enough to make it easy (some interfacing for I/O etc would have to be done).  It worked out well for HP however, as this pushed them into an entirely new, and emerging market.

In 1966 HP released the 16-bit HP 2100 (later to be renamed the HP 1000 series).  It was a design that had begun under Union Carbide’s Data Systems Inc, a company HP had recently acquired.  This gave HP a head start, and allowed them to evolve the design to meet their needs (at the time mostly to control instruments).  When released it included not only the hardware but a completely function software suite as well, including a FORTRAN compiler.  They initially ran with a 10MHz clock and a 1.6usec memory cycle time.

Throughout the 1970’s the design evolved, and would lead to many computers.  The 98xx desktop systems using HP’s NMOS BPC Hybrid processor were based on the HP 1000 series.  The design was a fairly simple accumulator based architecture with 2 16-bit accumulators (A and B) and a 15-bit PC and 68-base instructions.  The first version was directly programmed but all subsequent versions were microprogrammed, making alterations and additions to the instruction set much easier, a feature that became important in keeping the HP 1000 around.

The A series were the HP 1000’s of the 1980’s.  Development began around 1980 and the first computers, the A600 and A700, were released in 1982.  These were some of the first LSI based processors for the line.  THe A600 processor was called the ‘Lightning.’  The name “Lightning” came from the Mark Twain quote “Thunder is good, thunder is great, but it is lightning that does all the work.” “Thunder” was a reference to the PDP 11/23, one of DEC’s newer machines at the time.  HP had went from considering using DEC’s computers to run instruments, to the 4th largest maker of such computers in only a decade.  Certainly a fact not lost on either company.

The A600 is an interesting design, it is of course microprogrammed, and is based on AMD AM2901B bit-slice processors, supported by a 2910 microsequencer, and the 2904 status/shift control unit.  The rest of the board is Schottky TTL, PALs, FPLAs. and ROMs.  Each HP 1000 instruction is microcoded into a 56-bit instruction for controlling the 2901’s 2904 and 2910.  These 56-bit instructions directly operation on the processor.  Certain bits interface with certain parts of each chip, so they are directly executed.

A600 – 56-bit microinstruction word directly operates on the hardware (click for LARGE version)

A series of PAL’s contain the microcoding, allowing for easy updating (at the time).  A standard A600 executed 182 standard HP 1000 instructions.  It could do so at a rate of 1 MIPS, with a cycle time of 227 nanoseconds.

Each 2901 is a 4-bit slice processor, and contains 4-bit registers and ALU’s.  The HP 1000 A and B registers are mapped directly to the R0 and R1 registers of the 2901’s and the Program counter resides in R15.  The PAL’s determine what HP 1000 instruction is being executed, and decode it into the proper 2901 assembly code, building the 56-bit instruction word.  This is one of the best examples of how the AMD 2901 (and other bit slicers) were designed to be used.  The end user has no idea, or need to know what is executing their HP 1000 code.  Its is decoded and send to the bit slicers for processing which then return the results to the proper place.  If new functions are needed a new processor does not need to be designed, simply add additional PAL code to decode the new instructions.  And that is exactly what HP did….

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National Semi SC/MP Test Board

National Semiconductor released the SC/MP (aka the SCAMP or ISP-8A-500) in 1974 as a low cost PMOS 8-bit processor.  Later the design was moved to an NMOS process resulting in higher clock speeds and simpler power supply requirements.  This version was known as the SC/MP II or the ISP-8A-600.  It was used well into the 1980’s.

This test board is designed to test with the PMOS or the NMOS versions of this chip.  It has power supplies and clocking for both the PMOS and NMOS versions and requires only the slide of a switch to change between them.

I have a couple in stock, $94.95 with FREE shipping.

More info and purchasing info on the SC/MP Test Board page.

AMD Socket A Test Board

Processors are tested at many steps in the manufacturing process.  Automated visual inspections are done at several steps during the wafer lithography stage, the individual chips are tested and marked on the wafer before slicing, and then final testing and speed grading during the assembly process.

This board is part of that final test stage,  It is designed to test Socket A (462) CPU’s, 20 at a time.  The board was made by a company called DynaVision in June of 2000, coinciding with the release of AMD’s first Socket A processors.  The board would be used in a test machine, and likely manually loaded with up to 20 processors.  This cannot be a FULL test of the processor as not all signals are brought out (so it may miss a package defect).  All the test, debug and JTAG signals are brought out from each socket, as well as the necessary voltages and CLK signals provided.

A connector by each socket supports, PS_ON, PWERON, ANODE and CATHODE signals, though I am not entirely sure what there are for.  Best guess is thermal management.  Also next to this is 2 signals labeled TEC1 and TEC2, naming that may suggest Peltier junction cooling.

AMD 20 socket test board, circa 2000

The board is labeled AMD 317-S6300 and FAB 30-21041B.  Fab 30 could suggest AMD’s Dresden Germany Fab, which would make this board even more interesting, as only a very few processors were assembled/tested at the fabs themselves.  Most production AMD processors were assembled and tested in Penang, Malaysia (since 1972).

Someone at AMD was certainly intimately familiar with the design and use of this board, and its part in AMD’s success in the market.  Now it occupies a few square feet of a wall at the CPU Shack Museum keeping its secrets to itself.