THE MPC821 - BUILT FOR PDAS

(August 28th 1995) As expected, Motorola launched its two new PowerPC
embedded chips last week. The MPC821 is designed for portable
electronics, such as PDAs and the like.

It is essentially two chips in one, a regular PowerPC core is bundled
with a Communications Processor Module (CPM)- essentially another RISC
processor specifically designed for signal processing applications and
peripheral control. Yes that's right, despite the previous hoo-haa about
how got the PowerPC architecture is at signal processing, when it comes
to real optimisation, the company still augments its capabilities with
extra silicon.

The MPC821's abilities look compelling, one engineer working with
Motorola describes it as "essentially a 603 and a 68360 rolled into one
with a DRAM controller, PCMCIA port, chip select logic and some other
stuff thrown in for good measure". The announcement of the chips is
bolstered by a statement from a statement from Dragon Systems - dozens
of the speech recognition world saying the chip will support real-time
continuous speech recognition. A PDA that can handle continuous speech
recognition? nice, assuming that you can cram enough RAM into the
machine to store the vocabulary. However S Mee Ling, VP for business
development at Dragon, and the executive quoted in the Motorola press
release, is not actually committing himself to porting the company's
software to the new chip, though he says he is "in discussion" with
companies interested in building PDAs based on the new chip

The PowerPC core of the MPC821 is the kind of stripped-down affair seen
in previous embedded parts; there is no floating point unit and it can
only issue a single instruction at a time, however it has a full
complement of internal instruction queues, meaning that it can do branch
folding, branch prediction with conditional pre-fetch, but without
conditional execution. The PowerPC core is integrated with separate 4K
Byte data and instruction caches, both two-way set associative.The
company says that it will deliver 33 Dhrystone MIPS at 25MHz and 52 MIPS
at 40MHz

The CPM includes a simple RISC processor with multiply-accumulate
hardware for DSP functions and a whole heap of I/O functionality.
Perhaps most important, are the two high-speed serial communications
channels that can handle any of several low-layer protocols, such as
LocalTalk or Ethernet. each channel comes with its own DMA controller.
In addition the CPM has to serial management controllers, a serial
peripheral interface and an interprocessor-integrated communications
controller.

Running at 25MHz and operating at 3.3V, the processor draws 526mW. It is
also possible at this clock speed to run the core of the chip at 2.2V,
which pulls the requirement down to 300mW. No figures are available for
power consumption at 40MHz. As with all other PowerPC embedded
processors, the MPC821 comes with the ability to power-down its various
functional units. At its deepest sleep level the processor only draws
40uW.

Elsewhere on the silicon, the processor has a memory interface which,
the company says offers a glueless link "to almost any memory device or
memory system". The on-board LCD can drive a variety of grey scale and
colour panels, while the PCMCIA controller, compliant with release 2.1
of the standard can support two independent slots.

The chip is currently sampling in limited qualities with general
sampling following next month and full production set for January 1996.
No formal pricing has been announced, however the company is muttering
about them costing about $70 a-piece in quantities of 10,000.