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Maynard, Mass. - Digital Semiconductor is quietly preparing enhancements
to the Alpha instruction set, readying the microprocessor for an assault
on commercial multimedia. Three new categories of instructions aimed at
improving motion-estimation algorithms will be added to future Alpha
processors, and will put a full range of multimedia features-including
desktop video conferencing, MPEG-2 video playback and video authoring-in
Alpha's range without the need for separate dedicated circuitry, the
company said. The new instructions are more limited in scope than the
MMX instruction set recently described by Intel Corp. for the P55C CPU,
but their specificity is intentional, according to Tim Counihan, product
manager for Digital Semiconductor (Hudson, Mass.), a division of Digital
Equipment Corp.
While in general, Digital adheres to Intel's MMX approach of "adding
more execution units to a superscalar design [to] let you perform signal-
processing operations at floating-point precision," Counihan said motion
estimation is an exception. "It is inherently a limited-precision, fixed-
point algorithm that lends itself very well to single-instruction,
multiple-data [SIMD] approaches. A search instruction using packed
pixel data has so much impact on software compression speed that it is
worth doing. We are talking about a minor change that can increase
motion-estimation performance by a factor of 15."
Digital has added three categories of instructions to the Alpha
instruction set. The first category includes byte- and word-clamping
instructions that suppress overflow and underflow in packed data types,
plus instructions to produce minimum and maximum values. These
instructions work together to permit saturating arithmetic on packed
data.
The second group of instructions includes byte and word pack and
unpack operations.
Its own category
The third category actually consists of just a single instruction, which
computes the sum of the absolute differences of the bytes or words
packed into the two operands. This pixel-difference instruction is used
to perform SIMD searches in motion-estimation algorithms.
Digital Semiconductor is claiming impressive results for the new
instructions. The company said a 21164 Alpha CPU using the instructions
could perform two-way H.320 or H.323 video conferencing at 15
frames/second using the full 352-by-288-pixel image resolution of the
computer interchange format (CIP), and G.728 audio compression, all in
software. Current Pentium machines, in comparison, are limited to 7
frames/s, quarter-CIF images and H.324 data rates, Digital said.
The new instructions will be implemented iii the 21164 and in all
future Alphas, according to Counihan, including the 30 SPECint-95 21264,
which is scheduled for release next year, and the low-cost 21164PC.
The 21164PC is designated to meet Intel head-on in cost for a desktop
PC running Microsoft software Augmented with the new instructions for
software video handling and the FX!32 object-code translator, the 21164PC
will be the primary weapon in Digital's thrust to capture a piece of the
commercial desktop computing market from the Intel architecture. The
21164PC is scheduled for a 1997 announcement.