==============================================================================
SunFlash 77.36

Sun Samples UltraSPARC Chipset

May 1995 John J. McLaughlin, Editor/Publisher flash@flashback.com
==============================================================================

SAN FRANCISCO -- May 24, 1995 -- Today at SunWorld '95, Sun
Microsystems' SPARC Technology Business announced its
high-performance UltraSPARC chipset. The UltraSPARC chipset includes
the basic control and interface circuitry to build an estimated 240
SPECint92 and 350 SPECfp92 UltraSPARC system. UltraSPARC chipset
samples will ship in June 1995. The chipset supports the newly
announced Net.Core SBus reference design and the high-performance
UltraSPARC Port Architecture (UPA).

-------------------------------------------------------------------------------

"The UltraSPARC base chipset represents a true system approach to design -- and
one that we will continue to expand with multiprocessing and alternative bus
chips in the future. By delivering all the system building blocks necessary for
a high bandwidth, low latency and low-cost system, we are making it easy for
designers to quickly tailor their UltraSPARC system for specific applications,"
stated Art Swift, vice president of marketing for Sun's SPARC Technology
Business. "The chipset reflects our expertise by addressing system concerns
including variable width buses to eliminate bottlenecks."

The UltraSPARC chipset consists of the Uniprocessor System Controller
(STP2200BGA), the Reset/Interrupt/Clock Controller (STP2210QFP), the UPA to
SBus Interface (STP2220BGA), and the Crossbar Switch-Uniprocessor (STP2230SOP).

* The Uniprocessor System Controller (USC) is the system's interface to the
UltraSPARC microprocessor, memory, the I/O interface and the system bus.
Its primary function is to regulate the flow of requests and data
throughout the entire system and to control resets to all system bus
clients. The device is housed in a 225-pin BGA (Ball Grid Array) package.

* The Reset/Interrupt/Clock Controller (RIC) supports the system reset,
interrupt, scan and clock control functions. The device is housed in a
160-pin QFP (Quad Flat Pack) package.

* The UPA to SBus Interface (U2S) is the primary connection between the
system bus and the I/O subsystem. It acts as the system bus interface, the
SBus interface, the interrupt dispatcher, and the internal logic
controller. It also supports ECC generation and detection on the system
data bus. The device is housed in a 372-pin BGA package.

* The Crossbar Switch-Uniprocessor (XB1) is a three-port crossbar switch
that acts as the bridge between three separate system buses -- for
example, the processor, memory data and I/O buses. The device is housed in
a 48-pin TSSOP (Thin Shrink Small Outline Package) package.

About The UltraSPARC Port Architecture

Leveraging the system design expertise of Sun Microsystems, Inc., the
UltraSPARC Port Architecture (UPA) is an advanced hardware system architecture
that complements the UltraSPARC microprocessor's performance. It is fully
compliant with the newly announced Net.Core System Architecture Specification.
The UPA hardware architecture centralizes critical functionality, considerably
reducing latencies to memory and shared data. By minimizing latencies in
several key areas, UPA delivers outstanding throughput, while its scalable
structure makes it a viable architecture for a broad range of applications. To
lower system design cost, the UPA interconnect architecture is tightly coupled
with mainstream, volume technologies. It also integrates important
capabilities, further reducing system design complexity and cost.

About UltraSPARC

Unveiled on September 19, 1994, the 64-bit UltraSPARC is the first processor to
deliver the multimedia and data movement requirements of today's and tomorrow's
networked systems. It is the industry's first processor with on-chip multimedia
support for desktop video-conferencing, real-time MPEG-2 decompression, video
effects and texture -mapped triangle rendering. Its high scalar and high data
throughput design enables UltraSPARC to move data at a peak rate of 1.3
GBytes/second and, while employing the VISual Instruction Set (VIS), it can
operate at a rate of 1.67 GOps/second. The 5.2 million transistor design is
fabricated by Texas Instruments, Inc. at its billion-dollar advanced CMOS
fabrication facility in Dallas, Texas. UltraSPARC is manufactured using Texas
Instruments' advanced EPIC3, 0.5 micron CMOS process. EPIC3 is a
high-performance, low-voltage (3.3 volts), four-layer metal CMOS process.
UltraSPARC is packaged in a 521-pin BGA package.

Pricing and Availability

UltraSPARC chipset samples will be available in June 1995. Production devices
will be available in Fall 1995 for $450 each in unit quantities of 1,000.

SPARC Technology Business, a division of Sun Microsystems, Inc., was formed in
April 1993 to develop, design and distribute SPARC technologies and products
worldwide. SPARC Technology Business' portfolio includes microprocessors,
chipsets, modules, boards, technology licenses, silicon and system packages and
consulting services. SPARC Technology Business has more than 400 employees
working in product development, engineering, marketing and international sales
and support. For more information on SPARC Technology Business, access
http://www.sun.com/stb via a commercial browser interface.