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SAN FRANCISCO, Calif., March 6, 1995 -- Hewlett-Packard Company, the leading supplier of RISC(1)-based systems, today announced the industry's most powerful microprocessor. Using a synergy of technologies, collectively termed "Intelligent Execution," the PA-8000 can deliver superior support for commercial and technical applications. The microprocessor demonstrates leading performance with an estimated >360 SPECint92, >550 SPECfp92 and more than 700 tps for a uniprocessor system. The enhanced full 64-bit PA-RISC(2) processor is designed to maintain full binary compatibility with all prior and future PA-RISC chips and hence ensure continued investment protection for customers.
HP detailed the PA-8000 in a presentation here at the COMPCON 95 technical conference.
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The PA-8000, with its record-breaking performance, is well-suited for "performance hungry" applications, including commercial transaction processing and decision support systems, which require increasingly high levels of performance; graphics applications, including multimedia, that need significant levels of floating-point performance; complex simulation workloads, such as those of genetic research or fluid analysis, which require the ability to process and analyze large amounts of data quickly; and other applications such as video servers, data warehousing and network management.
The chip supports a high-performance 960 MB/s memory-processor-I/O "runway" bus with a 64-bit multiplexed address/data split. This bus is designed to maximize subsystem performance and also allows the PA-8000 to access very large amounts of main memory.
The current industry-leading TPC benchmarks have been achieved on PA-RISC systems using the PA-7100 processor. A 12-way symmetric multiprocessing (SMP) HP 9000 Model T500 in a client/server configuration recently posted a transaction rate of 4,067.17 transactions per minute (tpmC(3)) at $725/tpmC, the industry's highest single-server TPC-C performance.
Performance with the PA-8000 is expected to eclipse the 700-transactions-per-second (tps) threshold for a uniprocessor system, which would enable PA-8000-based systems to surpass the above multiprocessor's record-breaking benchmarks by greater than 50 percent. The PA-8000 yields approximately 60 percent higher in tps than IBM's estimate for its PowerPC 620 and 100 percent higher in tps than Sun's estimate for its UltraSPARC.
"Precision Architecture continues to lead the industry in performance and price/performance, as demonstrated by our industry-leading system benchmark results," said Richard W. Sevcik, HP vice president and general manager of the Systems Technology Group. "Today's announcement of the PA-8000 puts an end to our competition's claims that they are the performance leaders. PA-RISC is clearly the computer industry's leading RISC architecture."
Intelligent Execution is based upon the PA-8000's out-of-order execution capability. This feature allows the PA-8000 to attain peak superscalar performance via instruction execution as data dependencies are resolved -- regardless of given sequential order. This capability, combined with the PA-8000's large number of instruction execution units, its sophisticated branch prediction and speculative execution capability, optimized cache organization and a high performance bus interface.
Contributing to the advanced performance of the PA-8000 is a rich set of functional units. It contains 10 instruction-execution units, including two integer arithmetic logic units (ALUs), two shift/merge units, two floating-point multiply/accumulate units, two divide/square root units and two load/store units.
The PA-8000's out-of-order execution design assigns instruction scheduling to the hardware rather than the complier, and better utilizes the functional units. Up to four instructions can be issued in a single clock cycle feeding the 56-entry Instruction Reorder Buffer. This keeps the large sets of functional units busy and effectively minimizes resource conflicts. The chip can examine the 56 instruction entries at one time and select a set of four that are ready to be executed. This lets the processor create significant instruction-level parallelism, something that the complier would not necessarily be able to accomplish.
Incorporated into the PA-8000 superscalar processor is full 64-bit functionality -- including flat addressing and computation for integers and floating point. The chip supports complete 32-bit application compatibility including flat- and segmented-addressing schemes. The PA-8000 is the first processor to implement the complete PA-RISC 64-bit architecture, and it provides full binary compatibility with all previous and future PA-RISC implementations.
The PA-8000 design is fabricated using .5 micron, 3.3V complementary metal-oxide semiconductor processes and is fully scalable to future smaller geometries.
The PA-8000 is scheduled to first appear in HP computer systems within the next 12 months.
"HP continues to design industry-leading systems that can meet and exceed customers' performance and technical needs. At the core of those systems is technology like the PA-8000," said Sevcik.
Demand for RISC-based computers has grown quickly since the first commercially available RISC products were shipped in the mid-1980s. According to the January 1995 issue of the newsletter "Inside the New Computer Industry," total RISC-systems revenue for 1994 was $29.3 billion (U.S.), with PA-RISC achieving the leadership position with 32.7 percent market share.
Currently, PA-RISC technology spans HP systems ranging from under-$4,000 (U.S.) workstations to large-scale, 12-way SMP systems with mainframe-class performance. This demonstrates PA-RISC's inherent scalability, a primary objective of its original architecture definition, and protects customers' hardware and software investments in this architecture.
HP is the second-largest computer supplier in the United States, with computer revenues in excess of $19.6 billion in its 1994 fiscal year.
Hewlett-Packard Company is a leading global manufacturer of computing, communications and measurement products and services recognized for excellence in quality and support. HP has 98,200 employees and had revenue of $25 billion in its 1994 fiscal year.
RISC stands for reduced instruction-set computing.
PA-RISC stands for Precision Architecture-reduced instruction-set computing.
TPC-C is a benchmark developed by the industrywide Transaction Processing Performance Council (TPC). The TPC-C benchmark defines a rigorous standard for calculating performance and price/performance measured by transaction per minute (tpmC) and $/tpmC, respectively. TPC-C is considered the best standard measure of OLTP performance.