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POWERFLASH - POWERPC 604 ANNOUNCED

As promised Motorola and IBM unveiled the PowerPC 604 processor
today. The 32bit processor has one floating point unit, but three
integer units - two for single clock cycle instructions, the other
for integer multiplication and division. The chip has estimated
SPECint92 and Specfp92 ratings of 160 and 165 respectively.

The MPC604 is already sampling in small quantities to highly favoured
customers, but general sampling is set to begin in the third quarter
with volume production set for Q4. IBM will manufacture the
processor at its Burlington, Vermont facility and Motorola at its
MOS-11 factory in Austin, Texas. No prices were given.

The processor is being manufactured in 0.5 micron CMOS, but it is
worth noting that the part does not use the new, smaller transistor
geometry that made its debut in the 100MHz MPC601. So expect smaller
604s in the future.

Aimed at the high-end desktop and server market, the new chip
consumes between 8 Watts and 10 Watts in normal use. A 'nap' mode
takes consumption down to around 400mW.

Other specifications:
*Number of transistors: 3.6 million
*Die Size: 12.4mm x 15.8mm
*Two separate 16k 4-way set associative instruction and data
caches.
*Dynamic Branch prediction with 64-entry fully associative branch
target address cache and 512 entry branch history table.
*Dispatch Unit has an 8-instruction buffer

The 604 has an onboard phase-locked loop (PLL) which allows the
processor to be drive at 1x, 1.5x, 2x or 3x the bus speed. The
estimated benchmark below was for a 100MHz processor being driven at
1.5x the 66MHz bus-speed.

The new performance comparison table looks like this:

Processor SPECint92 SPECfp92
|MPC 601 50MHz 51 63
66 62 80
80 80 105
100 110 130
MPC 604 100MHz 160 165
MPC 603 66 MHz 60 70
80 75 85
Pentium 90 MHz 90 72.7
100 100 80.6

 

 

 

 

 

The MPC604 figures assume a compiler optimised for the new chip. We
will have a full assessment of the processor in the next issue of
PowerPC News (April 29th).

 

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